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OMAP3530-HiRel датащи(PDF) 17 Page - Texas Instruments

номер детали OMAP3530-HiRel
подробное описание детали  OMAP3525-HiRel and OMAP3530-HiRel Applications Processors
PDF  239 Pages
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производитель  TI [Texas Instruments]
домашняя страница  http://www.ti.com
Logo TI - Texas Instruments

OMAP3530-HiRel датащи(HTML) 17 Page - Texas Instruments

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OMAP3525-HiRel and OMAP3530-HiRel Applications Processors
www.ti.com
SPRS599 – JUNE 2009
Table 2-1. Ball Characteristics (CBB Pkg.) (continued)
BALL
BALL
PIN
MODE [4]
TYPE [5]
BALL
BALL
RESET
POWER [9]
HYS
BUFFER
PULL
IO
BOTTOM [1]
TOP [2]
NAME [3]
RESET
RESET
REL.
[10]
STRENGTH
U/D
CELL [13]
STATE [6]
REL.
MODE [8]
(mA) [11]
TYPE
STATE [7]
[12]
gpio_70
4
IO
safe_mode
7
AH22
NA
dss_data1
0
IO
L
L
7
VDDS
Yes
8
PU/ PD
LVDS/ CMOS
uart1_rts
2
O
gpio_71
4
IO
safe_mode
7
AG23
NA
dss_data2
0
IO
L
L
7
VDDS
Yes
8
PU/ PD
LVDS/ CMOS
gpio_72
4
IO
safe_mode
7
AH23
NA
dss_data3
0
IO
L
L
7
VDDS
Yes
8
PU/ PD
LVDS/ CMOS
gpio_73
4
IO
safe_mode
7
AG24
NA
dss_data4
0
IO
L
L
7
VDDS
Yes
8
PU/ PD
LVDS/ CMOS
uart3_rx_ irrx
2
I
gpio_74
4
IO
safe_mode
7
AH24
NA
dss_data5
0
IO
L
L
7
VDDS
Yes
8
PU/ PD
LVDS/ CMOS
uart3_tx_ irtx
2
O
gpio_75
4
IO
safe_mode
7
E26
NA
dss_data6
0
IO
L
L
7
VDDS
Yes
8
PU/ PD
LVCMOS
uart1_tx
2
O
gpio_76
4
IO
safe_mode
7
F28
NA
dss_data7
0
IO
L
L
7
VDDS
Yes
8
PU/ PD
LVCMOS
uart1_rx
2
I
gpio_77
4
IO
safe_mode
7
F27
NA
dss_data8
0
IO
L
L
7
VDDS
Yes
8
PU/ PD
LVCMOS
gpio_78
4
IO
safe_mode
7
G26
NA
dss_data9
0
IO
L
L
7
VDDS
Yes
8
PU/ PD
LVCMOS
gpio_79
4
IO
safe_mode
7
AD28
NA
dss_data10
0
IO
L
L
7
VDDS
＝Yes
8
PU/ PD
LVDS/ CMOS
gpio_80
4
IO
safe_mode
7
AD27
NA
dss_data11
0
IO
L
L
7
VDDS
Yes
8
PU/ PD
LVDS/ CMOS
gpio_81
4
IO
safe_mode
7
AB28
NA
dss_data12
0
IO
L
L
7
VDDS
Yes
8
PU/ PD
LVDS/ CMOS
gpio_82
4
IO
safe_mode
7
AB27
NA
dss_data13
0
IO
L
L
7
VDDS
Yes
8
PU/ PD
LVDS/ CMOS
gpio_83
4
IO
safe_mode
7
AA28
NA
dss_data14
0
IO
L
L
7
VDDS
Yes
8
PU/ PD
LVDS/ CMOS
gpio_84
4
IO
safe_mode
7
AA27
NA
dss_data15
0
IO
L
L
7
VDDS
Yes
8
PU/ PD
LVDS/ CMOS
gpio_85
4
IO
safe_mode
7
G25
NA
dss_data16
0
IO
L
L
7
VDDS
Yes
8
PU/ PD
LVCMOS
gpio_86
4
IO
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TERMINAL DESCRIPTION
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