TMS418160A

1048576 BY 16-BIT

DYNAMIC RANDOM-ACCESS MEMORY

SMKS891C – AUGUST 1996 – REVISED OCTOBER 1997

3

POST OFFICE BOX 1443

functional block diagram

A0

A1

A9

32

16

16

Timing and Control

Column -

Address

Buffers

Row -

Address

Buffers

I/O

Buffers

Data-

In

Reg.

Data-

Out

Reg.

Column Decode

Sense Amplifiers

R

o

w

D

e

c

o

d

e

256K Array

256K Array

256K Array

256K Array

256K Array

256K Array

DQ0 – DQ15

RAS UCAS

W

OE

LCAS

16 of 32

Selection

32

10

10

10

32

32

operation

dual xCAS

Two xCAS pins (LCAS and UCAS) are provided to give independent control of the 16 data I/O pins

(DQ0 – DQ15), with LCAS corresponding to DQ0 – DQ7 and UCAS corresponding to DQ8 – DQ15. Each xCAS

going low enables its corresponding DQx pin.

DQ pins.

Different modes of operation for upper and lower bytes in one cycle are not allowed, such as the example shown

in Figure 1.

RAS

UCAS

LCAS

W

Delayed write

Early write

Figure 1. Illegal Dual-xCAS Operation