TMS418160A

1048576 BY 16-BIT

DYNAMIC RANDOM-ACCESS MEMORY

SMKS891C – AUGUST 1996 – REVISED OCTOBER 1997

17

POST OFFICE BOX 1443

PARAMETER MEASUREMENT INFORMATION

RAS

UCAS

LCAS

Address

W

DQ8 –

DQ15

DQ0 –

DQ7

OE

tRASP

tRP

tRSH

tCRP

tPC

tCSH

tRCD

tCAS

tCP

tCAL

tRAL

tCAH

tASR

tRAH

tRAD

tCWL

tCWL

tRWL

tDH

tDS

Don’t Care

Don’t Care

Don’t Care

Don’t Care

Don’t Care

Column

Column

Valid In

Valid In

Valid In

Row

tCLCH

tASC

tWCH

tRHCP

(see Note A)

Don’t Care

Don’t Care

tWCS

(see Note D)

(see Note D)

(see Note E)

(see Note E)

(see Note F)

tCAS

NOTES: A. To hold the address latched by the first xCAS going low, the parameter tCLCH must be met.

B. A read cycle or read-modify-write cycle can be mixed with the write cycles as long as the read- and read-modify-write timing

specifications are not violated.

C. xCAS order is arbitrary.

D. tWCS and tWCH must be satisfied for each xCAS.

E. tDS and tDH for a DQ is referenced to the corresponding xCAS.

F. tCWL must be satisfied for each xCAS.

Figure 9. Enhanced-Page-Mode Early Write-Cycle Timing