TMS418160A

1048576 BY 16-BIT

DYNAMIC RANDOM-ACCESS MEMORY

SMKS891C – AUGUST 1996 – REVISED OCTOBER 1997

5

POST OFFICE BOX 1443

data out (DQ0 – DQ15)

Data out is the same polarity as data in. The output is in the high-impedance (floating) state until xCAS and OE

address) are satisfied. The delay time from xCAS low to valid data out is measured from each individual xCAS

to its corresponding DQx pin.

output enable (OE)

OE controls the impedance of the output buffers. When OE is high, the buffers remain in the high-impedance

state. Bringing OE low during a normal cycle activates the output buffers, putting them in the low-impedance

state. It is necessary for both RAS and xCAS to be brought low (until either OE or xCAS is brought high) for the

output buffers to go into the low-impedance state.

RAS-only refresh

A refresh operation must be performed once every 16 ms to retain data. This can be achieved by strobing each

of the 1 024 rows (A0 – A9). A normal read or write cycle refreshes all bits in each row that is selected. A RAS-only

operation can be used by holding both xCAS at the high (inactive) level, conserving power as the output buffers

remain in the high-impedance state. Externally generated addresses must be used for a RAS-only refresh.

hidden refresh

Hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished by holding

refresh cycle. The external address is ignored, and the refresh address is generated internally.

xCAS-before-RAS (xCBR) refresh

cycling RAS. The external address is ignored and the refresh address is generated internally.

power up

To achieve proper device operation, an initial pause of 200

µs, followed by a minimum of eight initialization

refresh (RAS-only or xCBR) cycle.