TMS418160A

1048576 BY 16-BIT

DYNAMIC RANDOM-ACCESS MEMORY

SMKS891C – AUGUST 1996 – REVISED OCTOBER 1997

12

POST OFFICE BOX 1443

PARAMETER MEASUREMENT INFORMATION

RAS

UCAS

LCAS

Address

W

DQ0 – DQ15

OE

Row

Column

Don’t Care

Valid Data In

tWC

tRAS

tRP

tCAS

tRCD

tT

tCP

tCRP

tRSH

tRAH

tASC

tCAL

tRAL

tRAD

tCAH

tCWL

tRWL

tWP

tDH

tOED

tOEH

tDS

tCLCH

Don’t Care

Don’t Care

tASR

(see Note A)

Don’t Care

Don’t Care

Don’t Care

tCSH

(see Note C)

NOTES: A. To hold the address latched by the first xCAS going low, the parameter tCLCH must be met.

B. xCAS order is arbitrary.

C. tCWL must be satisfied for each xCAS to write properly to each byte.

Figure 4. Write-Cycle Timing