TMS418160A

1048576 BY 16-BIT

DYNAMIC RANDOM-ACCESS MEMORY

SMKS891C – AUGUST 1996 – REVISED OCTOBER 1997

4

POST OFFICE BOX 1443

enhanced page mode

Page-mode operation allows faster memory access by keeping the same row address while selecting random

column addresses. The time for row-address setup and hold and address multiplexing is eliminated. The

maximum number of columns that can be accessed is determined by the maximum RAS low time and the xCAS

page-mode cycle time used. With minimum xCAS page-cycle time, all columns can be accessed without

intervening RAS cycles.

Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling

edge of RAS. The buffers act as transparent or flow-through latches while xCAS is high. The falling edge of the

first xCAS latches the column addresses. This performance improvement is referred to as enhanced-page

mode. This feature allows the devices to operate at a higher data bandwidth than conventional page-mode

because data retrieval begins as soon as the column address is valid rather than when xCAS transitions low.

column addresses for the next page cycle are valid at the time xCAS goes high, minimum access time for the

address: A0 – A9

Twenty address bits are required to decode each of the 1 048 576 storage cell locations. Twelve row-address

bits are set up on A0 through A11 and latched onto the chip by RAS. Eight column-address bits are set up on

A0 through A7 and latched onto the chip by the first xCAS. All addresses must be stable on or before the falling

edge of RAS and xCAS. RAS is similar to a chip enable in that it activates the sense amplifiers as well as the

row decoder. xCAS is used as a chip select, activating its corresponding output buffer and latching the address

bits into the column-address buffers.

The column address is latched on the first xCAS falling edge with address setup and hold parameters

referenced to that edge. In order to latch in a new column address, both xCAS pins must be brought high. The

edge of the new cycle. Keeping a column address valid while toggling xCAS requires a minimum hold time,

write enable ( W )

Read- or write mode is selected through W. A logic high on W selects the read mode and a logic low selects

the write mode. Data in is disabled when the read mode is selected. When W goes low prior to xCAS (early write),

data out remains in the high-impedance state for the entire cycle, permitting a write operation independent of

the state of OE. This permits early-write operations to be completed with OE grounded.

data in (DQ0 – DQ15)

Data is written during a write- or read-modify-write cycle. Depending on the mode of operation, the falling edge

of xCAS or W strobes data into the on-chip data latch. In an early-write cycle, W is brought low prior to a xCAS

falling edge and the data is strobed into the on-chip data latch for the corresponding DQs with setup-and-hold

times referenced to this xCAS signal.

In a delayed-write- or read-modify-write cycle, xCAS is already low and the data is strobed in by W with setup

and hold times referenced to this signal. Also, OE must be high to bring the output buffers to the high-impedance