GC4014 datasheet(36/46 Pages) TI

36 / 46 page

GRAYCHIP, INC.

- 31 -

APRIL 27, 1999

GC4014 QUAD RECEIVER CHIP

DATA SHEET REV 0.6

This document contains information which may be changed at any time without notice

7.0

APPLICATION NOTES

7.1

POWER AND GROUND CONNECTIONS

The GC4014 chip is a very high performance chip which requires solid power and ground connections to

avoid noise on the VCC and GND pins. If possible the GC4014 chip should be mounted on a circuit board with

dedicated power and ground planes and with at least two decoupling capacitors (0.01 and 0.1

µf) adjacent to each

GC4014 chip. If dedicated power and ground planes are not possible, then the user should place decoupling

capacitors adjacent to each VCC and GND pair.

IMPORTANT

The GC4014 chip may not operate properly if these power and ground guidelines are violated.

7.2

STATIC SENSITIVE DEVICE

The GC4014 chip is fabricated in a high performance CMOS process which is sensitive to the high voltage

transients caused by static electricity. These parts can be permanently damaged by static electricity and should only

be handled in static free environments.

7.3

SYNCHRONIZING MULTIPLE GC4014 CHIPS

A system containing two or more GC4014 chips will need to be synchronized if coherent operation is

desired. To synchronize multiple GC4014 chips connect all of the sync input pins together so they can be driven by

a common sync strobe. The common sync strobe can be from an external source, or can be the sync output from

one of the chips. If the sync output from one of the chips is used, then the user can choose to output a one shot sync

pulse from that chip, or the terminal count from the chip’s sync counter. If the terminal count is used, then the sync

cycle must be a multiple of 8N and the FLUSH (Address 9), NCO_SYNC and DITHER_SYNC (Address 24 of each

channel page) syncs must be set to “never” (see Table 4) after initial synchronization.

7.4

THERMAL MANAGEMENT

The junction temperature must be kept below 125

°C for reliable operation. The chip’s power dissipation

should be calculated using the equation for supply current in Section 6.5 and then the chip’s junction temperature

can be calculated using the package’s thermal conductivity shown in Section 6.3. At full rate operation (FCK=62.5)

the power is 1.3 Watts and the junction to ambient rise is 32 degrees per Watt for the plastic package. This

represents a rise of 42 degrees over ambient. This means that under these conditions the ambient temperature has

to be less than 83

°C. Air flow will decrease the thermal resistance by 10% to 40%, allowing ambient temperatures

between 87

°C and 100 °C. Increasing the decimation ratio (N) or decreasing the number of active channels (A) will

also allow a higher ambient temperature.

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