GRAYCHIP, INC.

- 5 -

APRIL 27, 1999

GC4014 QUAD RECEIVER CHIP

DATA SHEET REV 0.6

This document contains information which may be changed at any time without notice

The PFIR will also, if desired, convert the complex output data to real. The complex to real conversion also

doubles the output sample rate so that the PFIR decimation is 1 or 2 in the real mode.

The PFIR filter is followed by a gain and output format circuit. The gain circuit allows the user to add an

additional 18 dB of gain in 0.14 dB steps. The output format circuit can also delete every other sample without

filtering. Anti-aliasing filtering must have already been performed (in the second stage filter). This is useful to achieve

deeper far-band rejection since the stopband performance of the CIC filter is a function of the decimation that follows

it.

3.3.1

The Numerically Controlled Oscillator (NCO)

The tuning frequency of each down converter is specified as a 32 bit word and the phase offset is specified

as a 16 bit word. The NCOs can be synchronized with NCOs on other chips. This allows multiple down converter

outputs to be coherently combined, each with a unique phase and amplitude. A block diagram of the NCO circuit is

shown in Figure 4.

Figure 4. NCO Circuit

the desired phase in radians ranging between 0 and 2

downconvert the signal. A negative tuning frequency can be used to upconvert the negative image of a real signal

(inverting the spectrum).

The NCO’s spur level is reduced to below -92 dBc through the use of phase dithering. The spectrums in

Figure 5 show the NCO spurs for an example tuning frequency before and after dithering has been turned on. Notice

that the spur level decreases from -82 dB to -105 dB.

Figure 5. Example NCO Spurs

32 BITS

15 BITS

32 BITS

FREQUENCY

WORD

SINE/COSINE

OUT

18 MSBs

5 BITS

14 MSBs

DITHER

GENERATOR

PHASE

OFFSET

16 BITS

SINE/COSINE

LOOKUP

TABLE

(a) Before Dithering

(b) After Dithering

-82 dB

-105 dB