GRAYCHIP, INC.

- 13 -

APRIL 27, 1999

GC4014 QUAD RECEIVER CHIP

DATA SHEET REV 0.6

This document contains information which may be changed at any time without notice

control counter can be synchronized to one of these sources. These syncs can also be output from the chip so that

multiple chips can be synchronized to the syncs coming from a designated “master” GC4014 chip.

3.10

DATA LATENCY

The latency through the chip, including all pipeline delays and filtering group delays, is shown in the

following table (N is the CIC filter’s decimation ratio, see Section 3.5, SI is the sync input to the chip, SO is the sync

output from the chip, and the RDY signal marks the beginning of each output frame, See Figure 10):

The last entry can be used to identify the group delay through the chip for time tagging events which pass

through the chip, where the time tag needs to be accurate to fractions of the output sample. Note that the overall

decimation in the complex output mode is one sample every 4N inputs. This means that the step edge will come out

21 samples plus (2N+15) clocks later. A good time tag algorithm would be to count the number of clock cycles

between the tagged input sample and the next RDY signal (the number D), and then tag the output sample that

comes 21 RDY signals later with a time tag which is adjusted by (D - 2N-15) clocks. To insure that the adjustment

is always positive, one would wait 22 RDY signals (22 outputs) and tag the sample with an adjustment of (D+2N-15)

clocks. Note that the output sample to be tagged is the sample that is output between the 22nd RDY signal and the

next RDY signal (see Figure 10).

3.11

DIAGNOSTICS

The chip has an internal ramp generator which can be used in place of the data inputs for diagnostics. An

internal checksum circuit generates a checksum of the output data to verify the chip’s operation. Section 7.7 gives

suggested checksum configurations and their expected checksums.

Besides the internal diagnostics, the chip can support board level testing, an output test configuration which

can help initial debug as well as production test is described in Section 7.8.

Table 3: Latency

FROM INPUT

TO OUTPUT

LATENCY

UNITS

COMMENT

SI

SO

3

Clocks

sync in to sync out, Register settings:

OUTPUT_SYNC = 1,SO_INT_MODE =0

SI

RDY

3.5N+9

Clocks

Sync in to first valid RDY out

IN[0:13] at RDY

OUT (First)

5

Outputs

Data sample input coincident with RDY, to the first output

affected by it

IN[0:13] at RDY

OUT (Midpoint)

22

Outputs

-to the closest midpoint output affected by IN

IN[0:13] at RDY

OUT (Last)

37

Outputs

-to the last output affected by IN

IN[0:13] at RDY

OUT

(Step Response)

86N+15

Clocks

Step function delay, step edge is input coincident with

RDY, to the step edge output