GC4014 datasheet(30/46 Pages) TI

30 / 46 page

GRAYCHIP, INC.

- 25 -

APRIL 27, 1999

GC4014 QUAD RECEIVER CHIP

DATA SHEET REV 0.6

This document contains information which may be changed at any time without notice

5.17

CHANNEL CONTROL PAGES (PAGES 4, 5, 6, 7)

Pages 4, 5, 6 and 7 contain the frequency, phase, gain and control settings for the four channels. To

configure channels A, B, C and D use pages 4, 5, 6 and 7 respectfully. All registers are read/write.

ADDRESSES 16, 17, 18, 19: Frequency

ADDRESS

NAME

DESCRIPTION

FREQ[0:7]

Byte 0 (LSBs) of FREQ

FREQ[8:15]

Byte 1 of FREQ

FREQ[16:23]

Byte 2 of FREQ

FREQ[24:31]

Byte 3 (MSBs) of FREQ

The 32 bit frequency control word is defined as:

FREQ = 232F/FCK

where F is the desired tuning frequency and FCK is the chip’s clock rate (not the CK2X rate). Use positive frequency

values to downconvert signals. Use negative frequency values to invert the signal’s spectrum. The 32 bit 2’s

complement frequency words are entered as four bytes, the least significant byte in the lowest address, the most

significant in the highest address.

ADDRESSES 20, 21: Phase

ADDRESS

NAME

DESCRIPTION

PHASE[0:7]

Byte 0 (LSBs) of PHASE

PHASE[8:15]

Byte 1 (MSBs) of PHASE

The 16 bit phase offset is defined as:

PHASE = 216P/2

where P is the desired phase in radian from 0 to 2

π.

ADDRESS 22: Gain

, suggested default = 0x80

ADDRESS

NAME

DESCRIPTION

G[0:7]

Byte 0 (LSBs) of G

The upper two bits of G are stored in control register 5. Note that G is only part of the chip’s gain and should

be used in conjunction with SCALE, BIG_SCALE and COARSE. See Sections 5.4 and 5.5 for details. See Section

7.9 for a discussion on how to optimally set the gain of the chip.

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