GC4014 datasheet(25/46 Pages) TI

25 / 46 page

GRAYCHIP, INC.

- 20 -

APRIL 27, 1999

GC4014 QUAD RECEIVER CHIP

DATA SHEET REV 0.6

This document contains information which may be changed at any time without notice

5.6

OUTPUT FORMAT REGISTER

This register controls the output bit serial format.

ADDRESS 6:

Output Format Register

, suggested default = 0x01

BIT

TYPE

NAME

DESCRIPTION

0-3 LSB

R/W

RATE[0:3]

The bit serial rate is set at FCK2

-RATE, where RATE can range from 0 to 10. If RATE=0,

the SCK pin will not toggle and the serial rate is equal to the clock rate.

R/W

PACKED

Puts the serial outputs into 32 bit transfer mode where each complex pair is packed

into 32 bit words. The complex pair is formatted as I word in the upper byte and the Q

word in the lower byte. Each word is formatted as MSB first.

R/W

CONTINUOUS

The serial clock normally stops when the last bit of each transmission is complete and

stays low until the next OSP.

R/W

SCK_POL

This bit inverts the polarity of the serial clock. Normally SOUT and SFS change on the

rising edge of SCK. They change on the trailing edge when this bit is set.

7 MSB

R/W

SFS_POL

The SFS signal is treated as active low when this bit is set. Otherwise the signal is

treated as active high.

5.7

OUTPUT MODE REGISTER

This register controls the output summation, multiplexing and rounding.

ADDRESS 7:

Output Mode Register

, suggested default = 0x00

BIT

TYPE

NAME

DESCRIPTION

0,1 LSB

R/W

SUM_MODE

The channel outputs are replaced by the sum of outputs as shown in Table 1 of

Section 3.5

2,3

R/W

MUX_MODE

The outputs are multiplexed as described in Section 3.6.2.

R/W

RND8

Round into the 8 MSBs of the 16 bit output words.

R/W

RND10

Round into the 10 MSBs of the 16 bit output words.

R/W

RND12

Round into the 12 MSBs of the 16 bit output words.

7 MSB

R/W

RND14

Round into the 14 MSBs of the 16 bit output words.

Only one round control bit can be set. If none are set the output is 16 bits. Bits below the rounding point are

set to zero.

5.8

BLANKING CONTROL REGISTER

This register controls the blanking mode.

ADDRESS 8:

Blank Control Register

, suggested default = 0x50, power up reset to 0.

BIT

TYPE

NAME

DESCRIPTION

0-3 LSB

R/W

BLANK_RATE

The number of zeroes to insert between each sample in the

blanking mode. Ranges from 0 to 15.

4,5

R/W

BLANK_SYNC

The sync selection from Table 4 for synchronizing the zero

stuffing.

R/W

OUTPUT_ENABLE

Turns on the serial output pins including SFS and SCK. RDY is

also turned on if LINK_MODE is off (See Section 5.2).

7 MSB

R/W

RAM_TEST

Used for factory tests. Should be kept low.

Blanking is turned on for each channel using the channel mode register in each channel’s control page.

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