AD5522JSVDZ datasheet(29/60 Pages) AD

29 / 60 page

AD5522

Rev. A | Page 29 of 60

THEORY OF OPERATION

The AD5522 is a highly integrated, quad per-pin parametric

measurement unit (PPMU) for use in semiconductor automated

test equipment. It provides programmable modes to force a pin

voltage and measure the corresponding current (FVMI) and to

force a pin current and measure the corresponding voltage. The

device is also capable of all other combinations, including force

high-Z and measure high-Z. The PPMU can force or measure a

voltage range of 22.5 V. It can force or measure currents up to

±80 mA per channel using the internal amplifier; the addition

of an external amplifier enables higher current ranges. All the

DAC levels required for each PMU channel are on chip.

FORCE AMPLIFIER

The force amplifier drives the analog output FOH, which drives

a programmed current or voltage to the DUT (device under

test). Headroom and footroom requirements for this amplifier

are 3 V on either end. An additional ±1 V is dropped across the

sense resistor when maximum (rated) current is flowing

through it.

The force amplifier is designed to drive DUT capacitances up

to 10 nF, with a compensation value of 100 pF. Larger DUT

capacitive loads require larger compensation capacitances.

Local feedback ensures that the amplifiers are stable when

disabled. A disabled channel reduces power consumption by

2.5 mA per channel.

COMPARATORS

Per channel, the DUT measured voltage or current is monitored

by two comparators configured as window comparators. Internal

DAC levels set the CPL (comparator low) and CPH (comparator

high) threshold values. There are no restrictions on the voltage

settings of the comparator highs and lows. CPL going higher

than CPH is not a useful operation; however, it does not cause

any problems with the device. CPOLx (comparator output low)

and CPOHx (comparator output high) are continuous time

comparator outputs.

Table 8. Comparator Output Function Using SPI Interface

Test Condition

CPOLx

CPOHx

VDUT or IDUT > CPH

VDUT or IDUT < CPH

VDUT or IDUT > CPL

VDUT or IDUT < CPL

CPH > VDUT or IDUT > CPL

When using the SPI interface, full comparator functionality is

available. When using the LVDS interface, the comparator

function is limited to one output per comparator, due to the

large pin count requirement of the LVDS interface.

When using the LVDS interface, the comparator output available

pins, CPO0 to CPO3, provide information on whether the meas-

ured voltage or current is inside or outside the set CPH and CPL

window. Information on whether the measurement was high or

low is available via the serial interface (comparator status register).

Table 9. Comparator Output Function Using LVDS Interface

Test Condition

CPOx Output

(CPL < (VDUT or IDUT)) and ((VDUT or IDUT) < CPH)

(CPL > (VDUT or IDUT)) or ((VDUT or IDUT) > CPH)

CLAMPS

Current and voltage clamps are included on chip, one clamp for

each PMU channel. The clamps protect the DUT in the event of

an open-circuit or short-circuit condition. Internal DAC levels

set the CLL (clamp low) and CLH (clamp high) levels. The clamps

work to limit the force amplifier if a voltage or current at the

DUT exceeds the set levels. The clamps also protect the DUT if

a transient voltage or current spike occurs when changing to a

different operating mode or when programming the device to a

different current range.

The voltage clamps are available while forcing current, and the

current clamps are available while forcing voltage. The user can

set up the clamp status using the serial interface (system control

Each clamp has a smooth, finite transition region between

normal (unclamped) operation and the final clamped level, and

an internal flag is activated within this transition zone. The

open-drain CGALM pin indicates whether one or more PMU

channels has clamped. The clamp status of an individual PMU

can be determined by polling the alarm status register using the

SPI or LVDS interface.

CLL should never be greater than CLH. For the voltage clamps,

there should be 500 mV between the CLL and CLH levels to

ensure that a region exists in the middle of the clamps where

both are off. Similarly, set current clamps ±250 mV away from 0 A.

The transfer function for voltage clamping in FI mode is

VCLL or VCLH = 4.5 × VREF × (DAC_CODE/216) −

(3.5 × VREF × (OFFSET_DAC_CODE/216)) + DUTGND

See the DAC Levels section for more information.

The transfer function for current clamping in FV mode is

ICLL or ICLH = 4.5 × VREF × ((DAC_CODE −

32,768)/216)/(RSENSE × MI_Amplifier_Gain)

where:

RSENSE is the sense resistor of the selected current range.

MI_Amplifier_Gain is the gain of the measure current

instrumentation amplifier, either 5 or 10.

Do not change clamp levels while the channel is in force mode

because this can affect the forced voltage or current applied to

the DUT. Similarly, the clamps should not be enabled or

disabled during a force operation.

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