AD5522JSVDZ datasheet(55/60 Pages) AD

55 / 60 page

AD5522

Rev. A | Page 55 of 60

APPLICATIONS INFORMATION

POWER-ON DEFAULT

The power-on default for all DAC channels is that the contents

of each M register are set to full scale (0xFFFF), and the contents

of each C register are set to midscale (0x8000). The contents of

the DAC X1 registers at power-on are listed in Table 35.

The power-on default for the alarm status register is 0xFFFFF0,

and the power-on default for the comparator status register is

0x400000. The power-on default values of the PMU register and

the system control register are shown in Table 36 and Table 37.

SETTING UP THE DEVICE ON POWER-ON

On power-on, default conditions are recalled from the power-

on reset register to ensure that each PMU and DAC channel is

powered up in a known condition. To operate the device, the

user must follow these steps:

Configure the device by writing to the system control

Calibrate the device to trim out errors, and load the

required calibration values to the gain (M) and offset (C)

registers. Load codes to each DAC input (X1) register.

When X1 values are loaded to the individual DACs, the

calibration engine calculates the appropriate X2 value and

stores it, ready for the PMU address to call it.

Load the required PMU channel with the required force

mode, current range, and so on. Loading the PMU channel

configures the switches around the force amplifier,

measure function, clamps, and comparators, and also acts

as a load signal for the DACs, loading the DAC register

with the appropriate stored X2 value.

Because the voltage and current ranges have individual

DAC registers associated with them, each PMU register

mode of operation calls a particular X2 register. Therefore,

only updates (that is, changes to the X1 register) to DACs

associated with the selected mode of operation are reflected

in the output of the PMU. If there is a change to the X1

value associated with a different PMU mode of operation,

this X1 value and its M and C coefficients are used to

calculate a corresponding X2 value, which is stored in the

correct X2 register, but this value is not loaded to the DAC.

Table 35. Default Contents of DAC Registers at Power-On

DAC Register

Default Value

Offset DAC

0xA492

FIN DAC

0x8000

CLL DAC

0x0000

CLH DAC

0xFFFF

CPL DAC

0x0000

CPH DAC

0xFFFF

Table 36. Power-On Default for System Control Register

Bit

Bit Name

Default Value

21 (MSB)

CL3

CL2

CL1

CL0

CPOLH3

CPOLH2

CPOLH1

CPOLH0

CPBIASEN

DUTGND/CH

GUARD ALM

CLAMP ALM

INT10K

GUARD EN

GAIN1

GAIN0

TMP ENABLE

TMP1

TMP0

LATCHED

Unused data bit

0 (LSB)

Unused data bit

Table 37. Power-On Default for PMU Register

Bit

Bit Name

Default Value

21 (MSB)

CH EN

FORCE1

FORCE0

Reserved

MEAS1

MEAS0

FIN

SF0

SS0

CPOLH

COMPARE V/I

LTMPALM

TMPALM

Unused data bit

0 (LSB)

Unused data bit

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