AD5522JSVDZ datasheet(41/60 Pages) AD

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AD5522

Rev. A | Page 41 of 60

presented before the calibration engine completes the first stage of

the last Channel X2 calculation, data may be lost.

For other writes, (PMU, system control registers, and so forth),

the write command should not be completed (SYNC returning

high) until BUSY returns high. This is necessary to ensure that

calibration data is not lost and that the calibration data is not

corrupted.

Table 17. BUSY Pulse Widths

Action

BUSY Pulse Width1

Loading Data to PMU, System Control

0.27 μs maximum

Loading X1 to 1 PMU DAC Channel

1.5 μs maximum

Loading X1 to 2 PMU DAC Channels

2.1 μs maximum

Loading X1 to 3 PMU DAC Channels

2.7 μs maximum

Loading X1 to 4 PMU DAC Channels

3.3 μs maximum

BUSY pulse width = ((number of channels + 1) × 600 ns) + 300 ns.

BUSY also goes low during a power-on reset and when a falling

edge is detected on the RESET pin.

WRITE 1

FIRST

STAGE

SECOND

STAGE

THIRD

STAGE

~600ns

600ns

CALIBRATION ENGINE TIME

FOR EXAMPLE,

WRITE TO 3 FIN

DAC REGISTERS

300ns

WRITE 2

FIRST

STAGE

SECOND

STAGE

THIRD

STAGE

FIRST

STAGE

SECOND

STAGE

THIRD

STAGE

FIRST

STAGE

SECOND

STAGE

THIRD

STAGE

Figure 53. Multiple Writes to DAC X1 Registers

Writing data to the system control register, the PMU control

digital calibration engine, thus speeding up configuration of the

device on power-on, but care should be taken not to issue these

commands while BUSY is low as previously described.

The value of the X2 register is calculated each time the user

writes new data to the corresponding X1 register. The calculation

is performed in a three-stage process. The first two stages take

approximately 600 ns each, and the third stage takes approxi-

mately 300 ns. When the write to the X1 register is complete,

the calculation process begins. If the write operation involves

the update of a single DAC channel, the user is free to write to

another X1 register, provided that the write operation does not

finish (SYNC returns high) until after the first-stage calculation

is complete, that is, 600 ns after the completion of the first write

operation.

WRITE 1

WRITE 2

WRITE 3

FIRST

STAGE

SECOND

STAGE

THIRD

STAGE

~600ns

600ns

CALIBRATION ENGINE TIME

300ns

FIRST

STAGE

SECOND

STAGE

THIRD

STAGE

FIRST

STAGE

SECOND

STAGE

THIRD

STAGE

Figure 54. Multiple Single Channel Writes Engaging the Calibration Engine

The serial word assignment consists of 29 bits. Bit 28 to Bit 22

are common to all registers, whether writing to or reading from

the device. The PMU3 to PMU0 data bits (Bit 27 to Bit 24) address

each PMU channel (or associated DAC register). When the

PMU3 to PMU0 bits are all zeros, the system control register

is addressed.

The mode bits, MODE0 and MODE1, address the different sets

of DAC registers and the PMU register.

Table 18. Mode Bits

B23

MODE1

B22

MODE0

Action

Write to the system control register or

the PMU register

Write to the DAC gain (M) register

Write to the DAC offset (C) register

Write to the DAC input data (X1) register

Readback Control, RD/WR

Setting the RD/WR bit (Bit 28) high initiates a readback

sequence of the PMU, alarm status, comparator status, system

control, or DAC register, as determined by the address bits.

PMU Address Bits: PMU3, PMU2, PMU1, PMU0

The PMU3 to PMU0 data bits (Bit 27 to Bit 24) address each

PMU channel on chip. These bits allow individual control of

each PMU channel or any combination of channels, in addition

to multichannel programming. PMU bits also allow access to

write registers such as the system control register and the DAC

registers, in addition to reading from all the registers (see Table 19).

NOP (No Operation)

If an NOP (no operation) command is loaded, no change is

made to DAC or PMU registers. This code is useful when

performing a readback of a register within the device (via the

SDO pin) where a change of DAC code or PMU function may

not be required.

Reserved Commands

Any bit combination that is not described in the register address

tables for the PMU, DAC, and system control registers indicates

a reserved command. These commands are unassigned and are

reserved for factory use. To ensure correct operation of the

device, do not use reserved commands.

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