AD5522JSVDZ datasheet(47/60 Pages) AD

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AD5522

Rev. A | Page 47 of 60

WRITE DAC REGISTER

The DAC input, gain, and offset registers are addressed through a combination of PMU bits (Bit 27 to Bit 24) and mode bits (Bit 23 and

Bit 22). Bit A5 to Bit A0 address each DAC level on chip. Bit D15 to Bit D0 are the DAC data bits used when writing to these registers. The

PMU address bits allow addressing of a particular DAC for any combination of PMU channels.

Table 26. DAC Register Bits

B28

B27

B26

B25

B24

B23

B22

B21

B20

B19

B18

B17

B16

B15 to B0

RD/WR

PMU3

PMU2

PMU1

PMU0

MODE1

MODE0

Data Bits[D15 (MSB):D0 (LSB)]

Table 27. DAC Register Functions

Bit

Bit Name

Description

28 (MSB)

RD/WR

When this bit is low, a write function takes place to the selected register; setting the RD/WR bit high

initiates a readback sequence of the PMU, alarm status, comparator status, system control, or DAC

PMU3

Bit PMU3 to Bit PMU0 address each PMU and DAC channel in the device. These bits allow control of

each individual DAC channel or any combination of channels, in addition to multichannel programming.

PMU2

PMU1

PMU0

MODE1

The MODE1 and MODE0 bits allow addressing of the DAC gain (M), offset (C), or input (X1) register.

MODE0

MODE1

MODE0

Action

Write to the system control register or the PMU register

Write to the DAC gain (M) register

Write to the DAC offset (C) register

Write to the DAC input data (X1) register

DAC Register Specific Bits

DAC address bits. The A5 to A3 bits select the register set that is addressed. See the DAC Addressing

section.

DAC address bits. The A2 to A0 bits select the DAC that is addressed. See the DAC Addressing section.

15 to 0

D15 (MSB) to D0 (LSB)

16 DAC data bits.

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