AD5522JSVDZ datasheet(34/60 Pages) AD

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AD5522

Rev. A | Page 34 of 60

DAC LEVELS

Each channel contains five dedicated DAC levels: one for the

force amplifier, one each for the clamp high and clamp low levels,

and one each for the comparator high and comparator low levels.

The architecture of a single DAC channel consists of a 16-bit

resistor-string DAC followed by an output buffer amplifier. This

resistor-string architecture guarantees DAC monotonicity. The

16-bit binary digital code loaded to the DAC register determines

at which node on the string the voltage is tapped off before

being fed into the output amplifier.

The transfer function for DAC outputs is as follows:

VOUT = 4.5 × VREF × (X2/216) − (3.5 × VREF ×

(OFFSET_DAC_CODE/216)) + DUTGND

where:

VREF is the reference voltage and is in the range of 2 V to 5 V.

X2 is the calculated DAC code value and is in the range

of 0 to 65,535 (see the Gain and Offset Registers section).

OFFSET_DAC_CODE is the code loaded to the offset DAC. It is

multiplied by 3.5 in the transfer function. On power-up, the

default code loaded to the offset DAC is 0xA492; with a 5 V

reference, this gives a span of ±11.25 V.

OFFSET DAC

The AD5522 is capable of forcing a 22.5 V (4.5 × VREF) voltage

span. Included on chip is one 16-bit offset DAC (one for all four

channels) that allows for adjustment of the voltage range.

The usable range is −16.25 V to +22.5 V. Zero scale loaded to

the offset DAC gives a full-scale range of 0 V to 22.5 V, midscale

gives ±11.25 V, and the most useful negative range is −16.25 V

to +6.25 V. Full scale loaded to the offset DAC does not give a

useful output voltage range, because the output amplifiers are

limited by the available footroom. Table 13 shows the effect of

the offset DAC on the other DACs in the device.

Table 13. Relationship of Offset DAC to Other DACs

(VREF = 5 V)

Offset DAC Code

DAC Code

DAC Output Voltage (V)

32,768

+11.25

65,535

+22.50

32,768

−8.75

32,768

+2.50

65,535

+13.75

42,130

−11.25

32,768

65,535

+11.25

60,855

−16.25

32,768

−5.00

65,535

+6.25

65,535

Footroom limitations

The power supplies should be selected to support the required

range and should take into account amplifier headroom and

footroom and sense resistor voltage drop (±4 V).

Therefore, depending on the headroom available, the input to

the force amplifier can be unipolar positive or bipolar, either

symmetrical or asymmetrical about DUTGND, but always

within a voltage span of 22.5 V.

The offset DAC offsets all DAC functions. It also centers the

current range so that zero current always flows at midscale

code, regardless of the offset DAC setting.

Rearranging the transfer function for the DAC output gives the

following equation to determine which offset DAC code is

required for a given reference and output voltage range.

OFFSET_DAC_CODE = (216 × (VOUT − DUTGND))/(3.5 ×

VREF) − ((4.5 × DAC_CODE)/3.5)

When the output range is adjusted by changing the default value

of the offset DAC, an extra offset is introduced due to the gain

error of the offset DAC channel. The amount of offset is depen-

dent on the magnitude of the reference and how much the

offset DAC channel deviates from its default value. See the

Specifications section for this offset. The worst-case offset

occurs when the offset DAC channel is at positive or negative

full scale. This value can be added to the offset present in the

main DAC channel to give an indication of the overall offset

for that channel. In most cases, the offset can be removed by

programming the C register of the channel with an appropriate

value. The extra offset caused by the offset DAC needs to be

taken into account only when the offset DAC is changed from

its default value.

GAIN AND OFFSET REGISTERS

Each DAC level has an independent gain (M) register and an

independent offset (C) register, which allow trimming out of

the gain and offset errors of the entire signal chain, including

the DAC. All registers in the AD5522 are volatile, so they must

be loaded on power-on during a calibration cycle. Data from

the X1 register is operated on by a digital multiplier and adder

controlled by the contents of the M and C registers. The

calibrated DAC data is then stored in the X2 register.

The digital input transfer function for each DAC can be

represented as follows:

X2 = [(M + 1)/2n × X1] + (C − 2n − 1)

where:

X2 is the data-word loaded to the resistor-string DAC.

X1 is the 16-bit data-word written to the DAC input register.

M is the code in gain register (default code = 216 − 1).

C is the code in offset register (default code = 215).

n is the DAC resolution (n = 16).

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