AD5522JSVDZ datasheet(48/60 Pages) AD

48 / 60 page

AD5522

Rev. A | Page 48 of 60

DAC Addressing

For the FIN and comparator (CPH and CPL) DACs, there is a

set of X1, M, and C registers for each current range, and one set

for the voltage range; for the clamp DACs (CLL and CLH),

there are only two sets of X1, M, and C registers.

When calibrating the device, the M and C registers allow volatile

storage of gain and offset coefficients. Calculation of the corres-

ponding DAC X2 register occurs only when the X1 data is loaded

(no internal calculation occurs on M or C updates).

There is one offset DAC for all four channels in the device that

is addressed using the PMUx bits. The offset DAC has only an

input register associated with it; no M or C registers are asso-

ciated with this DAC. When writing to the offset DAC, set the

MODE1 and MODE0 bits high to address the DAC input

The same address table is also used for readback of a particular

DAC address.

Note that CLL is clamp level low and CLH is clamp level high.

•

When forcing a voltage, the current clamps are engaged;

therefore, both the CLL current ranges register set and the

CLH current ranges register set are loaded to the clamp DACs.

•

When forcing a current, the voltage clamps are engaged;

therefore, both the CLL voltage range register set and the

CLH voltage range register set are loaded to the clamp DACs.

All codes not explicitly referenced in this table are reserved and

should not be used.

Table 28. DAC Register Addressing

MODE1

MODE0

Addressed Register

Offset DAC X

±5 μA current range

FIN M

FIN C

FIN X1

±20 μA current range

FIN M

FIN C

FIN X1

±200 μA current range

FIN M

FIN C

FIN X1

±2 mA current range

FIN M

FIN C

FIN X1

±external current range

FIN M

FIN C

FIN X1

Voltage range

FIN M

FIN C

FIN X1

Current ranges

CLL M

CLL C

CLL X11

Voltage range

CLL M

CLL C

CLL X11

Current ranges

CLH M

CLH C

CLH X12

Voltage range

CLH M

CLH C

CLH X12

±5 μA current range

CPL M

CPL C

CPL X1

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