 |
поискавой системы для электроныых деталей |
|
|
поискавой системы для электроныых деталей |
|
7906 датащи(PDF) 82 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
7906 датащи(HTML) 82 Page - Renesas Technology Corp |
|
|
82 / 531 page  7906 Group User’s Manual Rev.2.0 6-3 INTERRUPTS Remarks Non-maskable Non-maskable software interrupt Do not use. Non-maskable internal interrupt Do not use. Maskable internal interrupts Maskable internal interrupts Maskable internal interrupts Maskable internal interrupt Maskable external interrupts Do not use. Non-maskable software interrupt Do not use. Maskable external interrupts 6.2 Interrupt sources Tables 6.2.1 and 6.2.2 list the interrupt sources and the interrupt vector addresses. When programming, set the start address of each interrupt routine to the vector addresses listed in these tables. 6.2 Interrupt sources Low-order address FFFE16 FFFC16 FFFA16 FFF816 FFF616 FFF416 FFF216 FFF016 FFEE16 FFEC16 FFEA16 FFE816 FFE616 FFE416 FFE216 FFE016 FFDE16 FFDC16 FFDA16 FFD816 FFD616 FFD416 FFD216 FFD016 FFCE16 FFCC16 FFCA16 FFC816 FFC616 FFC416 FFC216 Interrupt vector addresses Table 6.2.1 Interrupt sources and interrupt vector addresses (1) High-order address FFFF16 FFFD16 FFFB16 FFF916 FFF716 FFF516 FFF316 FFF116 FFEF16 FFED16 FFEB16 FFE916 FFE716 FFE516 FFE316 FFE116 FFDF16 FFDD16 FFDB16 FFD916 FFD716 FFD516 FFD316 FFD116 FFCF16 FFCD16 FFCB16 FFC916 FFC716 FFC516 FFC316 Interrupt source Reset Zero division BRK instruction (Note) DBC (Note) Watchdog timer Reserved area Reserved area Reserved area Reserved area Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 Timer B0 Timer B1 Timer B2 UART0 receive UART0 transmit UART1 receive UART1 transmit A-D conversion INT3 INT4 Reserved area Reserved area Address matching detection Reserved area INT5 INT6 INT7 Note: The BRK instruction and the DBC interrupt are used exclusively for a debugger. q Maskable interrupt: An interrupt of which request’s acceptance can be disabled by software. q Non-maskable interrupt (including zero division, watchdog timer, and address matching detection interrupts): An interrupt which is certain to be accepted when its request occurs. These interrupts do not have their interrupt control registers and are not affected by the interrupt disable flag (I). Reference 3. RESET 7900 Series Software Manual 14. WATCHDOG TIMER 7. TIMER A 8. TIMER B 11. SERIAL I/O 12. A-D CONVERTER 6.10 External interrupts 17. DEBUG FUNCTION 6.10 External interrupts |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Russian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
