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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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7906 датащи(PDF) 38 Page - Renesas Technology Corp |
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7906 датащи(HTML) 38 Page - Renesas Technology Corp |
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38 / 531 page  7906 Group User’s Manual Rev.2.0 2-17 CENTRAL PROCESSING UNIT (CPU) (Note 2) Port P5 register (Note 2) Port P5 direction register Port P6 register Port P7 register Port P6 direction register Port P7 direction register (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) Address UART1 transmit/receive mode register Address UART0 transmit/receive mode register UART0 baud rate register (BRG0) UART0 transmit/receive control register 0 UART0 transmit/receive control register 1 UART0 transmit buffer register UART1 transmit/receive control register 0 UART1 baud rate register (BRG1) UART1 transmit/receive control register 1 UART0 receive buffer register UART1 transmit buffer register UART1 receive buffer register 016 116 216 316 416 516 616 716 816 916 A16 B16 C16 D16 E16 F16 1016 1116 1216 1316 1416 1516 1616 1716 1816 1916 1A16 1B16 1C16 1D16 1E16 1F16 2016 2116 2216 2316 2416 2516 2616 2716 2816 2916 2A16 2B16 2C16 2D16 2E16 2F16 3016 3116 3216 3316 3416 3516 3616 3716 3816 3916 3A16 3B16 3C16 3D16 3E16 3F16 4016 4116 4216 4316 4416 4516 4616 4716 4816 4916 4A16 4B16 4C16 4D16 4E16 4F16 5016 5116 5216 5316 5416 5516 5616 5716 5816 5916 5A16 5B16 5C16 5D16 5E16 5F16 6016 6116 6216 6316 6416 6516 6616 6716 6816 6916 6A16 6B16 6C16 6D16 6E16 6F16 7016 7116 7216 7316 7416 7516 7616 7716 7816 7916 7A16 7B16 7C16 7D16 7E16 7F16 A-D register 0 A-D register 1 A-D register 2 A-D register 3 A-D register 4 (Note 2) Port P1 register (Note 2) Port P1 direction register Port P2 register (Note 2) Port P2 direction register (Note 2) A-D control register 0 A-D control register 1 A-D conversion interrupt control register UART0 transmit interrupt control register UART0 receive interrupt control register UART1 transmit interrupt control register UART1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register (Note 2) (Note 2) (Note 2) Timer A clock division select register Processor mode register 0 Processor mode register 1 Watchdog timer register Watchdog timer frequency select register INT3 interrupt control register INT4 interrupt control register One-shot start flag 0 Up-down flag 0 Count start flag 0 Timer A0 register Timer A1 register Timer A2 register Timer A3 register Timer A4 register Timer B0 register Timer B1 register Timer B2 register Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register Address (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) External interrupt input read register D-A control register D-A register 0 D-A register 1 8016 8116 8216 8316 8416 8516 8616 8716 8816 8916 8A16 8B16 8C16 8D16 8E16 8F16 9016 9116 9216 9316 9416 9516 9616 9716 9816 9916 9A16 9B16 9C16 9D16 9E16 9F16 Particular function select register 0 Particular function select register 1 Particular function select register 2 (Note 2) Debug control register 0 Debug control register 1 Notes 1: Do not read from and write to this register. 2: Do not write to this register. 3: When these registers are accessed, set the address compare register access enable bit (bit 2 at address 6716) to “1.” (Refer to “CHAPTER 17. DEBUG FUNCTION.”) 4: This register is assigned only to the flash memory version. (Refer to “CHAPTER 19. FLASH MEMORY VERSION.”) Nothing is assigned here in the mask ROM version. Address compare register 0 (Note 3) Address compare register 1 (Note 3) (Note 1) (Note 1) Flash memory control register (Note 4) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) Count start flag 1 One-shot start flag 1 2.4 Memory assignment Fig. 2.4.2 SFR area’s memory map (1) |
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