7733 datasheet(210/940 Pages) RENESAS

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SERIAL I/O

7733 Group User’s Manual

8–7

(1) Internal/External clock selection bit (bit 3)

q Clock synchronous serial I/O mode

When an internal clock is selected by clearing this bit to “0,” a clock which is specified with the BRG

count source selection bits (bits 1 and 0 at addresses 3416, 3C16 and 6816) becomes the count

source of BRGi (described later). At this time, the BRGi’s output divided by 2 is the transfer clock.

The transfer clock is output from the CLKi pin (Note).

When an external clock is selected by setting this bit to “1,” a clock input to the CLKi pin becomes

the transfer clock.

Note : When selecting an internal clock and performing only transmission in UART0, the number

of the transfer clock output pins varies according to the contents of the transmit clock output

pin selection bits (bits 5 and 4 at address 6E16). (Refer to section “8.3.1 Transfer clock.”)

q UART mode

When an internal clock is selected by clearing this bit to “0,” a clock which is specified with the BRG

count source selection bits (bits 1 and 0 at addresses 3416, 3C16 and 6816) becomes the count

source of the BRGi (described later). At this time, the CLKi pin functions as a programmable I/O

port.

When an external clock is selected by setting this bit to “1,” a clock input to the CLKi pin becomes

the count source of BRGi .

Note that, in the UART mode, the BRGi’s output divided by 16 is always the transfer clock.

BRGi: UARTi baud rate register (Refer to section “8.2.7 UARTi baud rate register (BRGi).”)

8.2 Block description

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