7733 datasheet(30/940 Pages) RENESAS

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OVERVIEW

7733 Group User’s Manual

1-3

ROM

RAM

Ports P0–P2, P4–P8

Port P3

Timers A0–A4

Timers B0–B2

UART0–UART2

Main-clock oscillation

circuit

Sub-clock oscillation

circuit

Input/Output withstand

voltage

Output current

Items

Number of basic instructions

The minimum instruction execution time

Main-clock frequency f(XIN)

Sub-clock frequency f(XCIN)

Memory size

Programmable I/O ports

Multifunction timers

Serial I/O

A-D converter

Watchdog timer

Interrupts

Clock generating circuits

Power source voltage

Power consumption in single-chip mode

Port input/output

characteristics

Memory expansion

Operating temperature range

Device structure

Package

1.1 Performance overview

Table 1.1.1 lists the M37733MHBXXXFP’s performance overview.

Table 1.1.1 M37733MHBXXXFP’s performance overview

Performance

103

160 ns

(When f(XIN) = 25 MHz and the main clock is the system clock)

25 MHz (Max.) (Note 3)

32.768 kHz (Typ.)

124 Kbytes

3968 bytes

8 bits ! 8

4 bits ! 1

16 bits ! 5

16 bits ! 3

(UART or clock synchronous serial I/O) ! 3

(10-bit successive approximation method) ! 1 (8 channels)

12 bits ! 1

3 external, 16 internal (By software, one of interrupt priority

levels 0 to 7 can be set for each interrupt)

Built-in (externally connected to a ceramic resonator or a

quartz-crystal oscillator.)

Built-in (externally connected to a quartz-crystal oscillator)

5 V

± 10% (When the main clock is the system clock)

2.7 V to 5.5 V (When the sub clock is the system clock)

47.5 mW (When f(XIN) = 25 MHz, VCC = 5 V, and the

main clock is the system clock, Typ.)

250

µW (When f(XCIN) = 32 kHz, VCC = 5 V, the sub clock

is the system clock, and the main clock is stopped, Typ.)

5 V

5 mA

Possible (Maximum of 16 Mbytes)

–20

°C to +85 °C

High-performance CMOS silicon gate process

80-pin plastic molded QFP

Notes 1: All of the 7733 Group microcomputers are the same except for package type, memory type,

memory size, and electrical characteristics.

2: For the low voltage version, refer to chapter “18. LOW VOLTAGE VERSION.”

3: When the main clock division selection bit = “1,” the maximum value of f(XIN) = 12.5 MHz.

1.1 Performance overview

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