7733 datasheet(208/940 Pages) RENESAS

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SERIAL I/O

7733 Group User’s Manual

8–5

Bit

Sleep selection bit

(Valid in the UART mode.) (Note)

Parity enable bit

(Valid in the UART mode.) (Note)

Odd/Even parity selection bit

(Valid in the UART mode when

the parity enable bit = “1.”)

(Note)

Stop bit length selection bit

(Valid in the UART mode.)

(Note)

Internal/External clock selection

bit

Serial I/O mode selection bits

Bit name

At reset

Functions

0 0 0: Serial I/O is disabled.

(P8 functions as a

programmable I/O port.)

0 0 1: Clock synchronous serial I/O

mode

0 1 0: Do not select.

0 1 1: Do not select.

1 0 0: UART mode

(Transfer data length = 7 bits)

1 0 1: UART mode

(Transfer data length = 8 bits)

1 1 0: UART mode

(Transfer data length = 9 bits)

1 1 1: Do not select.

UART0 transmit/receive mode register (address 30 16)

UART1 transmit/receive mode register (address 38 16)

Note: Bits 4 to 6 are ignored in the clock synchronous serial I/O mode. (They may be “0” or “1.”)

Fix bit 7 to “0.”

b2 b1 b0

0: Odd parity

1: Even parity

0: Parity is disabled.

1: Parity is enabled.

0: The sleep mode is terminated. (Ignored.)

1: The sleep mode is selected.

0: Internal clock

1: External clock

0: One stop bit

1: Two stop bits

8.2.1 UARTi transmit/receive mode register

Figures 8.2.2 and 8.2.3 show the structure of UARTi transmit/receive mode register. The serial I/O mode

selection bits are used to select a UARTi’s operating mode. For bits 4 to 6, refer to section “8.4.2 Transfer

data format.” For bit 7, refer to section “8.4.8 Sleep mode.”

Fig. 8.2.2 Structure of UARTi transmit/receive mode register (1)

8.2 Block description

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