7733 datasheet(94/940 Pages) RENESAS

94 / 940 page

7733 Group User's Manual

4–15

INTERRUPTS

INTACK sequence

: CPU’s standard clock

: High-order 8 bits of CPU address bus

: Middle-order 8 bits of CPU address bus

: Low-order 8 bits of CPU address bus

: Data bus for CPU’s odd address

: Data bus for CPU’s even address

qWhen stack pointer (S)’s contens is even

CPU

PCH

FF16

ADH

PCH

PSH

PCL

PSL

ADH

ADL

PCL

!!16

Interrupt disable

flag (I)

CPU

ADL

([S]–1)H ([S]–2)H ([S]–3)H ([S]–4)H ([S]–5)H ([S]–5)H

[S]H

([S]–1)L ([S]–2)L ([S]–3)L ([S]–4)L ([S]–5)L ([S]–5)L

[S]L

Op-code

FF16

!!16

[S]

!!16

ADH

ADL

: Contents of stack pointer (S)

: Low-order 8 bits of vector address

: Contents of vector address (High-order address)

: Contents of vector address (Low-order address)

: Not used

Fig. 4.7.2 INTACK sequence’s timing

Table 4.7.1 Change in IPL at acceptance of interrupt request

Change in IPL

Level 0 (0002) is set.

Level 7 (1112) is set.

Not changed

Accepted interrupt’s priority level is set.

Interrupt source

Reset

Watchdog timer interrupt

Zero division interrupt

BRK instruction interrupt

Other interrupts

4.7 How interrupts are processed

4.7.1 Change in IPL at acceptance of interrupt request

When an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set to the

processor interrupt priority level (IPL). This operation makes the processing for multiple interrupts easy.

(Refer to section “4.9 Multiple interrupts.”

At reset or when a watchdog timer interrupt or software interrupt is accepted, a value listed in Table 4.7.1

is set into IPL.

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