7733 datasheet(209/940 Pages) RENESAS

209 / 940 page

In the clock synchronous serial I/O mode, bits 4 to 6 are ignored. (They may be “0” or “1.”)

SERIAL I/O

7733 Group User’s Manual

8–6

Bit

Not implemented.

Parity enable bit

(Valid in the UART mode.) (Note 2)

Odd/Even Parity selection bit

(Valid in the UART mode when the

parity enable bit = “1”.)

(Note 2)

(Valid in the UART mode.) (Note 2)

Internal/External clock selection

bit

Serial I/O mode selection bits

(Note 1)

Bit name

At reset

Un-

defined

Functions

0 0 0: Serial I/O is ignored.

(P7 functions as a

programmable I/O port)

0 0 1: Clock synchronous serial I/O

mode

0 1 0:

0 1 1:

1 0 0: UART mode

(Transfer data length = 7 bits)

1 0 1: UART mode

(Transfer data length = 8 bits)

1 1 0: UART mode

(Transfer data length = 9 bits)

1 1 1: Do not select.

UART2 transmit/receive mode register (address 64 16)

Notes 1: By specifying these bits, an A-D conversion interrupt or a UART2 transmit/receive interrupt

is selected.

When bits 2 to 0 = “0002,” an A-D conversion interrupt is selected. When bits 2 to 0 = “001 2”

or “1002 to 1112,” a UART2 transmit/receive interrupt is selected.

b2 b1 b0

0: Odd parity

1: Even parity

0: Parity is disabled.

1: Parity is enabled.

0: Internal clock

1: External clock

0: One stop bit

1: Two stop bits

Do not select.

—

8.2 Block description

Fig. 8.2.3 Structure of UARTi transmit/receive mode register (2)

Stop bit length selection bit

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