HD6432351 datasheet(441/1025 Pages) RENESAS

441 / 1025 page

Section 9 I/O Ports

Rev. 3.00 Sep 15, 2006 page 407 of 988

REJ09B0330-0300

• Mode 1 [H8S/2350]; modes 1 and 2 [H8S/2351]

Pin PG4 functions as a bus control output pin (CS0) when the corresponding PGDDR bit is set

to 1, and as an input port when the bit is cleared to 0.

For pins PG3 to PG0, setting the corresponding PGDDR bit to 1 makes the pin an output port,

while clearing the bit to 0 makes the pin an input port.

• Modes 3 and 7 [H8S/2351 only]

Setting a PGDDR bit to 1 makes the corresponding port G pin an output port, while clearing

the bit to 0 makes the pin an input port.

• Modes 4 and 5 [H8S/2350]; modes 4, 5, and 6 [H8S/2351]

Pins PG4 to PG1 function as bus control output pins (CS0 to CS3) when the corresponding

PGDDR bits are set to 1, and as input ports when the bits are cleared to 0.

Pin PG0 functions as the CAS output pin when DRAM interface is designated. Otherwise,

setting the corresponding PGDDR bit to 1 makes the pin an output port, while clearing the bit

to 0 makes the pin an input port. For details of the DRAM interfaces, see section 6, Bus

Controller.

Port G Data Register (PGDR)

—

Undefined

—

Undefined

—

Undefined

—

PG4DR

R/W

PG3DR

R/W

PG0DR

R/W

PG2DR

R/W

PG1DR

R/W

Bit

Initial value

R/W

PGDR is an 8-bit readable/writable register that stores output data for the port G pins (PG4 to

PG0).

Bits 7 to 5 are reserved; they return an undetermined value if read, and cannot be modified.

PGDR is initialized to H'00 (bits 4 to 0) by a power-on reset, and in hardware standby mode. It

retains its prior state after a manual reset, and in software standby mode.

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