M32CSLASH8A datasheet(216/372 Pages) RENESAS

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M32C/8A Group

17. Serial Interfaces

Rev.1.00

Jul 15, 2007

Page 199 of 352

REJ09B0385-0100

Figure 17.3

U0SMR to U4SMR Registers

b6 b5 b4

Symbol

U0SMR to U2SMR

U3SMR, U4SMR

Address

0367h, 02E7h, 0337h

0327h, 02F7h

After Reset

00h

Function

Bit Symbol

Bit Name

BBS

ABC

IICM

ACSE

SSS

Set to 0

Reserved bit

Transmit start condition

select bit(3)

I2C mode select bit

ABSCS

−

(b3)

0: Rising edge of serial clock

1: Timer Aj underflow (j = 0, 3, 4)(4)

0 : Not related to RXDi

1 : Synchronized with RXDi

Bus conflict detect

sampling clock select bit(3)

0: No auto clear function

1: Auto cleared when bus conflict occurs

Auto clear function select

bit for transmit enable bit(3)

Clock division synchronous

bit(5,6)

0: External clock not divided

1: External clock divided by 2

SCLKDIV

UARTi Special Mode Register (i = 0 to 4)

Arbitration lost detect flag

control bit(1)

Bus busy flag(1, 2)

0: Updated per bit

1: Updated per byte

0: Stop condition detected (bus is free)

1: Start condition detected (bus is busy)

0 : Other than I2C mode

1 : I2C mode

NOTES:

1. These bits are used in I2C mode.

2. The BBS bit is set to 0 by writing a 0. Writing a 1 has no effect.

3. These bits are used in IE mode.

4. UART0: Timer A3 underflow signal, UART1: Timer A4 underflow signal,

UART2: Timer A0 underflow signal, UART3: Timer A3 underflow signal,

UART4: Timer A4 underflow signal.

5. The SCLKDIV bit is used in GCI mode.

6. Refer to the note for the SU1HIM bit in the UiSMR2 register.

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