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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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M16C/29 датащи(PDF) 282 Page - Renesas Technology Corp |
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M16C/29 датащи(HTML) 282 Page - Renesas Technology Corp |
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282 / 499 page  16. MULTI-MASTER I2C bus INTERFACE p u o r G 9 2 / C 6 1 M page 258 8 5 4 f o 7 0 0 2 , 0 3 .r a M 2 1 . 1 . v e R 2 1 1 0 - 1 0 1 0 B 9 0 J E R Figure 16.3 S00 and S20 Registers 0: Standard clock mode 1: High-speed clock mode 0: ACK is returned 1: ACK is not returned 0: No ACK clock 1: With ACK clock ACK Clock Bit ACK Bit SCL Mode Specification Bit SCL Frequency Control Bits CCR0 CCR1 CCR2 CCR3 CCR4 FAST MODE ACKBIT ACK-CLK Function Bit Name Bit Symbol 0016 After Reset 02E416 Address Symbol S20 b6 b5 b4 b3 b2 b1 b0 C0 Clock Control Register I2 RW See Table 16.3 RW RW RW RW RW RW RW RW Symbol Address After Reset S00 02E016 XX16 b7b6b5b4b3b2b1b0 RW Function RW(1) NOTE: 1. Write is enabled only when the ES0 bit in the S1D0 register is 1 (I2C bus interface is enabled). Write the transmit data after the receive data is read because the S00 register is used to store both the transmit and receive data. When the S00 register is set, bits BC2 to BC0 in the S1D0 register are set to 0002, while bits LRB, AAS, and AL in the S10 register are set to 0 respectively. Transmit/receive data are stored. In master transmit mode, the start condition/stop condition are triggered by writing data to the register (refer to 16.9 START Condition Generation Method and 16.11 STOP Condition Generation Method ). Start transmitting/receiving data while synchronizing with SCL I2C0 Data Shift Register |
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