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M16C/29 датащи(PDF) 279 Page - Renesas Technology Corp

номер детали M16C/29
подробное описание детали  RENESAS MCU M16C FAMILY / M16C/Tiny SERIES
PDF  499 Pages
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
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M16C/29 датащи(HTML) 279 Page - Renesas Technology Corp

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16. MULTI-MASTER I2C bus INTERFACE
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Item
Function
Format
Based on Philips I2C bus standard:
7-bit addressing format
High-speed clock mode
Standard clock mode
Communication mode
Based on Philips I2C bus standard:
Master transmit
Master receive
Slave transmit
Slave receive
SCL clock frequency
16.1kHz to 400kHz (at VIIC (1)= 4MHz)
I/O pin
Serial data line
SDAMM(SDA)
Serial clock line
SDLMM(SCL)
16. Multi-master I2C bus Interface
The multi-master I2C bus interface is a serial communication circuit based on Philips I2C bus data transfer
format, equipped with arbitration lost detection and synchronous functions. Figure 16.1 shows a block
diagram of the multi-master I2C bus interface and Table 16.1 lists the multi-master I2C bus interface func-
tions.
The multi-master I2C bus interface consists of the S0D0 register, the S00 register, the S20 register, the
S3D0 register, the S4D0 register, the S10 register, the S2D0 register and other control circuits.
Figures 16.2
to 16.8 show the registers associated with the multi-master I2C bus.
Table 16.1 Multi-master I2C bus interface functions
NOTE:
1. VIIC=I2C system clock



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