M16CSLASH29 datasheet(243/499 Pages) RENESAS

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14. Serial I/O

page 219

Item

Specification

Transfer data format

• Transfer data length: 8 bits

Transfer clock

• The SMi6 bit in the SiC (i=3, 4) register is set to 1 (internal clock) : fj/ (2(n+1))

fj = f1SIO, f2SIO, f8SIO, f32SIO. n=Setting value of SiBRG register

0016 to FF16.

• SMi6 bit is set to 0 (external clock) : Input from CLKi pin (1)

Transmission/reception

• Before transmission/reception can start, the following requirements must be met

start condition

Write transmit data to the SiTRR register (2, 3)

• When the SMi4 bit in the SiC register is set to 0

The rising edge of the last transfer clock pulse (4)

• When SMi4 is set to 1

The falling edge of the last transfer clock pulse (4)

CLKi pin fucntion

I/O port, transfer clock input, transfer clock output

SOUTi pin function

I/O port, transmit data output, high-impedance

SINi pin function

I/O port, receive data input

Select function

• LSB first or MSB first selection

Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7

can be selected

• Function for setting an SOUTi initial value set function

When the SMi6 bit in the SiC register is set to 0 (external clock), the SOUTi pin

output level while not tranmitting can be selected.

• CLK polarity selection

Whether transmit data is output/input timing at the rising edge or falling edge of

transfer clock can be selected.

NOTE:

1. To set the SMi6 bit in the SiC register to 0 (external clock), follow the procedure described below.

• If the SMi4 bit in the SiC register is set to 0, write transmit data to the SiTRR register while input on the CLKi

pin is high. The same applies when rewriting the SMi7 bit in the SiC register.

• If the SMi4 bit is set to 1, write transmit data to the SiTRR register while input on the CLKi pin is low. The same

applies when rewriting the SMi7 bit.

• Because shift operation continues as long as the transfer clock is supplied to the SI/Oi circuit, stop the transfer

clock 2. Unlike UART0 to UART2, SI/Oi (i = 3 to 4) is not separated between the transfer register and buffer.

Therefore, do not write the next transmit data to the SiTRR register during transmission.

3. When the SMi6 bit in the SiC register is set to 1 (internal clock), SOUTi retains the last data for a 1/2 transfer

clock period after completion of transfer and, thereafter, goes to a high-impedance state. However, if transmit

data is written to the SiTRR register during this period, SOUTi immediately goes to a high-impedance state, with

the data hold time thereby reduced.

4. When the SMi6 bit in the SiC register is set to 1 (internal clock), the transfer clock stops in the high state if the

SMi4 bit is set to 0, or stops in the low state if the SMi4 bit is set to 1.

Table 14.20 SI/O3 and SI/O4 Specifications

Interrupt request

generation timing

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