M16CSLASH29 datasheet(222/499 Pages) RENESAS

222 / 499 page

14. Serial I/O

page 198

Table 14.11 Registers to Be Used and Settings in I2C bus mode (1) (Continued)

Bit

Function

Master

Slave

U2TB

0 to 7

Set transmission data

U2RB(1) 0 to 7

Reception data can be read

ACK or NACK is set in this bit

ABT

Arbitration lost detection flag

Invalid

OER

Overrun error flag

U2BRG 0 to 7

Set bit rate

Invalid

U2MR(1) SMD2 to SMD0

Set to 0102

CKDIR

Set to 0

Set to 1

IOPOL

Set to 0

U2C0

CLK1, CLK0

Select the count source for the U2BRG

Invalid

CRS

Invalid because CRD = 1

TXEPT

Transmit buffer empty flag

CRD

Set to 1

NCH

Set to 1

CKPOL

Set to 0

UFORM

Set to 1

U2C1

Set this bit to 1 to enable transmission

Transmit buffer empty flag

Set this bit to 1 to enable reception

Reception complete flag

U2IRS

Invalid

U2RRM,

Set to 0

U2LCH, U2ERE

U2SMR IICM

Set to 1

ABC

Select the timing at which arbitration-lost Invalid

is detected

BBS

Bus busy flag

3 to 7

Set to 0

U2SMR2 IICM2

Refer to Table 14.13

CSC

Set this bit to 1 to enable clock

Set to 0

synchronization

SWC

Set this bit to 1 to have SCL2 output

fixed to L at the falling edge of the 9th

fixed to “L” at the falling edge of the 9th

bit of clock

ALS

Set this bit to 1 to have SDA2 output

Set to 0

stopped when arbitration-lost is detected

STAC

Set to 0

Set this bit to 1 to initialize UART2 at

start condition detection

SWC2

Set this bit to 1 to have SCL2 output

forcibly pulled low

SDHI

Set this bit to 1 to disable SDA2 output

Set to 0

U2SMR3 0, 2, 4 and NODC Set to 0

Set to 0

CKPH

Refer to Table 14.13

DL2 to DL0

Set the amount of SDA2 digital delay

NOTE:

1. Not all bits in the register are described above. Set those bits to 0 when writing to the registers in I2C bus mode.

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