M16CSLASH29 datasheet(206/499 Pages) RENESAS

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14.Serial I/O

page 182

Table 14.3

lists pin functions for the case where the multiple transfer clock output pin select function is

deselected. Table 14.4 lists the P64 pin functions during clock synchronous serial I/O mode.

Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi

pin outputs an “H”. (If the N-channel open-drain output is selected, this pin is in a high-impedance state.)

Table 14.3 Pin Functions

(When Not Select Multiple Transfer Clock Output Pin Function)(1)

Table 14.4 P64 Pin Functions(1)

Pin Name

Function

Method of Selection

TxDi (i = 0 to 2)

(P63, P67, P70)

Serial data output

Serial data input

Transfer clock output

Transfer clock input

I/O port

(Outputs dummy data when performing reception only)

RxDi

(P62, P66, P71)

CLKi

(P61, P65, P72)

Set the CKDIR bit in the UiMR register to 0

Set the CKDIR bit in the UiMR register to 1

Set the PD6_1 bit and PD6_5 bit in the PD6 register, and the PD7_2 bit in the

PD7 register to 0

Set the PD6_2 bit and PD6_6 bit in the PD6 register, and PD7_1 bit in the PD7

Set the CRD bit in the UiC0 register to 0

Set the CRS bit in the UiC0 register to 0

Set the PD6_0 bit and PD6_4 bit in the PD6 register is set to 0, the PD7_3 bit

in the PD7 register to 0

Set the CRD bit in the UiC0 register to 0

Set the CRS bit in the UiC0 register to 1

Set the CRD bit in the UiC0 register to 1

CTS input

RTS output

CTSi/RTSi

(P60, P64, P73)

NOTE:

1: When the U1MAP bit in PACR register is 1 (P73 to P70), UART1 pin is assgined to P73 to P70.

Pin Function

Bit Set Value

U1C0 register

UCON register

PD6 register

CRD

CRS

RCSP

CLKMD1

CLKMD0

PD6_4

P64

Input: 0, Output: 1

CTS1

RTS1

CTS0(2)

CLKS1

1(3)

NOTES:

1. When the U1MAP bit in PACR register is 1 (P73 to P70), this table lists the P70 functions.

2. In addition to this, set the CRD bit in the U0C0 register to 0 (CT00/RT00 enabled) and the CRS bit in the

U0C0 register to 1 (RTS0 selected).

3. When the CLKMD1 bit is set to 1 and the CLKMD0 bit is set to 0, the following logic levels are output:

• High if the CLKPOL bit in the U1C0 register is set to 0

• Low if the CLKPOL bit in the U1C0 register is set to 1

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