M16CSLASH29 datasheet(200/499 Pages) RENESAS

200 / 499 page

14.Serial I/O

page 176

UARTi Transmit/receive Control Rregister 0 (i=0 to 2)

Symbol

Address

After Reset

U0C0 to U2C0

03A416, 03AC16, 037C16

000010002

b7 b6 b5 b4 b3 b2 b1 b0

Function

TXEPT

CLK1

CLK0

CRS

CRD

NCH

CKPOL

BRG count source

select bit(7)

Transmit register empty

flag

0 : Transmit data is output at falling edge of transfer clock

and receive data is input at rising edge

1 : Transmit data is output at rising edge of transfer clock

and receive data is input at falling edge

CLK polarity select bit

CTS/RTS function

select bit

CTS/RTS disable bit

Data output select bit(5)

0 0 : f1SIO or f2SIO is selected

0 1 : f8SIO is selected

1 0 : f32SIO is selected

1 1 : Do not set

b1 b0

0 : LSB first

1 : MSB first

0 : Data present in transmit register (during transmission)

1 : No data present in transmit register

(transmission completed)

0 : CTS/RTS function enabled

1 : CTS/RTS function disabled

(P60, P64 and P73 can be used as I/O ports)(6)

0 : TxD2/SDA2 and SCLi pins are CMOS output

1 : TxD2/SDA2 and SCLi pins are N-channel open-drain output(4)

UFORM Transfer format select bit

(2)

Effective when CRD is set to 0

0 : CTS function is selected (1)

1 : RTS function is selected

Bit Name

Bit

Symbol

(3)

NOTES:

1. Set the corresponding port direction bit for each CTSi pin to 0 (input mode).

2. Effective when bits SMD2 to SMD0 in the UMR register to 0012 (clock synchronous serial I/O mode) or 0102 (UART mode transfer

data 8 bits long). Set the UFORM bit to 1 when bits SMD2 to SMD0 are set to 1012 (I2C bus mode) and 0 when they are set to 1002.

3. CTS1/RTS1 can be used when the CLKMD1 bit in the UCON register is set to 0 (only CLK1 output) and the RCSP bit in the UCON

4. SDA2 and SCL2 are effective when i = 2.

5. When bits SMD2 to SMD in the UiMR regiser are set to 0002 (serial I/O disable), do not set NCH bit to 1 (TxDi/SDA2 and SCL2 pins

are N-channel open-drain output).

6. When the U1MAP bit in PACR register is 1 (P73 to P70), P70 functions as CTS/RTS pin in UART1.

7. When the CLK1 and CLK0 bit settings are changed, set the UiBRG register.

UART Transmit/receive Control Register 2

Symbol

Address

After Reset

UCON

03B016

X00000002

b7 b6 b5 b4 b3 b2 b1 b0

Bit Name

Bit

Symbol

Function

CLKMD0

CLKMD1

Nothing is assigned. If necessary, set to 0.

When read, the content is undefined

U0IRS

U1IRS

U0RRM

U1RRM

RCSP

(b7)

0 : Output from CLK1 only

1 : Transfer clock output from multiple pins function selected

Effective when the CLKMD1 bit is set to 1

0 : Clock output from CLK1

1 : Clock output from CLKS1

0 : Transmit buffer empty (Tl = 1)

1 : Transmission completed (TXEPT = 1)

0 : Transmit buffer empty (Tl = 1)

1 : Transmission completed (TXEPT = 1)

0 : Continuous receive mode disabled

1 : Continuous receive mode enable

0 : Continuous receive mode disabled

1 : Continuous receive mode enabled

UART1 transmit

interrupt cause select

UART0 continuous

receive mode enable bit

UART0 transmit interrupt

cause select bit

UART1 continuous

receive mode enable bit

UART1 CLK/CLKS

select bit 0

UART1 CLK/CLKS

select bit 1 (1)

Separate UART0

CTS/RTS bit

0 : CTS/RTS shared pin

1 : CTS/RTS separated (P64 pin functions as CTS0 pin )

(2)

NOTES:

1. When using multiple transfer clock output pins, make sure the following conditions are met:set the CKDIR bit in the U1MR

2. When the U1MAP bit in PACR register is set to 1 (P73 to P70), P70 pin functions as CTS0 pin.

Figure 14.6 U0C0 to U2C0 and UCON Registers

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