M16CSLASH29 datasheet(187/499 Pages) RENESAS

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13. Timer S

page 163

Figure 13.22 Single-phase Waveform Output Mode

FFFF16

fBT1

65536-m

fBT1

Inverse

65536

fBT1

When setting to 0,

write 0 by program

Base timer

(1) Free-running operation

(The RST4, RST2, and RST1 bits in the G1BCR0 and G1BCR1 registers are set to 0)

(2) The base timer is reset when the base timer matches either following register

(a) G1PO0 (enabled by setting bit RST1 to 1, and bits RST4 and RST2 to 0), or

(b) G1BTRR (enabled by setting bit RST4 to 1, and bits RST2 and RST1 to 0)

000016

OUTC1j pin

G1IRj bit

j=0 to 7

m : Setting value of the G1POj register

G1IRj bit : Bits in the G1IR register

OUTC1j pin

FFFF16

n+2

Base timer

000016

Inverse

fBT1

n+2-m

fBT1

Inverse

n+2

fBT1

Return to default output level

Write 0 by program

if setting to 0

Return to default

output level

Inverse

j=1 to 7

m : Setting value of the G1POj register

n: Setting value of either G1PO0 register or G1BTRR register

G1IRj bit : Bits in the G1IR register

The above applies under the following conditions.

-The IVL bit in the G1POCRj register is set to 0 ("L" output as a default value) and the INV

bit is set to 0 (not inversed).

-Bits UD1 to UD0 are set to 002 (counter increment mode).

The above applies under the following conditions.

-The IVL bit in the G1POCRj register is set to 0 ("L" output as a default value) and the INV bit is set to 0

(not inversed).

-Bits UD1 to UD0 are set to 002 (counter increment mode).

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