M16CSLASH29 datasheet(186/499 Pages) RENESAS

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13. Timer S

page 162

13.5.1 Single-Phase Waveform Output Mode

Output signal level of the OUTC1j pin becomes high ("H") when the INV bit in the G1POCRj (j=0 to 7)

value. The "H" signal switches to a low-level ("L") signal when the base timer reaches 000016. Table 13.8

lists specifications of single-phase waveform mode. Figure 13.22 lists an example of single-phase wave-

form mode operation.

Table 13.8 Single-phase Waveform Output Mode Specifications

Item

Specification

Output waveform

• Free-running operation

(bits RST1, RST2, and RST4 of registers G1BCR1 and G1BCR0 are set to 0

(no reset))

Cycle

Default output level width :

Inverse level width

• The base timer is cleared to 000016 by matching the base timer with either

following register

(a) G1PO0 register (enabled by setting RST1 bit to 1, and RST4 and RST2 bits to 0), or

(b) G1BTRR register (enabled by setting RST4 bit to 1, and RST2 and RST1 bits to 0)

Cycle

Default output level width :

Inverse level width

m : setting value of the G1POj register (j=0 to 7), 000116 to FFFD16

n : setting value of the G1PO0 register or the G1BTRR register, 000116 to FFFD16

Waveform output start condition

The IFEj bit in the G1FE register is set to 1 (channel j function enabled)

Waveform output stop condition

The IFEj bit is set to 0 (channel j function disabled)

Interrupt request

The G1IRj bit in the G1IR register is set to 1 when the base timer value

matches the G1POj register value (See Figure 13.22)

OUTC1j pin (1)

Pulse signal output pin

Selectable function

• Default value set function: Set starting waveform output level

• Inverse output function: Waveform output signal is inversed and provided

from the OUTC1j pin

fBT1

65536-m

fBT1

n+2

fBT1

n+2-m

fBT1

65536

fBT1

NOTE:

1. Pins OUTC10 to OUTC17.

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