M16CSLASH29 datasheet(167/499 Pages) RENESAS

167 / 499 page

13. Timer S

page 143

Figure 13.3 G1DV Register and G1BCR1 Register

Divider Register

Symbol

Address

After Reset

G1DV

032A16

0016

b7 b6 b5 b4 b3 b2 b1 b0

Function

Setting range

Divide f1, f2 or two-phase pulse input by (n+1)

for fBT1 clock cycles generation.

n: the setting value of the G1DV register

0016 to FF16

RST1

0: The base timer is not reset by

applying "L" to the INT1 pin

1: The base timer is reset by applying "L"

to the INT1 pin

Base Timer Control Register 1

Symbol

Address

After Reset

G1BCR1

032316

0016

Bit Name

Function

Bit

Symbol

(b0)

RST2

BTS

UD0

UD1

Base timer reset

cause select bit 1

Base timer reset

cause select bit 2

Counter increment/

decrement control bit

0: Base timer is reset

1: Base timer starts counting

: Counter increment mode

: Counter increment/decrement mode

: Two-phase pulse signal processing

mode

: Do not set to this value

NOTS:

1. The base timer is reset two fBT1 clock cycles after the base timer matches the value set in the

G1PO0 register. (See Figure 13.7 for details on the G1PO0 register) When the RST1 bit is set to 1,

the value of the G1POj register (j=1 to 7) for the waveform generating function must be set to a

value smaller than that of the G1PO0 register.

When the RST1 bit is set to 1, set the RST4 bit in the G1BCR0 register to 0.

Reserved bit

Set to 0

0: The base timer is not reset by

matching the G1PO0 register

1: The base timer is reset by matching

with the G1PO0 register (1)

Reserved bit

Set to 0

Reserved bit

Set to 0

(b3)

(b7)

Base timer start bit

b7 b6 b5 b4 b3 b2 b1 b0

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