M16CSLASH29 datasheet(165/499 Pages) RENESAS

165 / 499 page

13. Timer S

page 141

Figure 13.1 IC/OC Block Diagram

BTS: Bits in the G1BCR1 register

CTS1 to CTS0, DF1 to DF0, GT, PR : Bits in the G1TMCRj register (j= 0 to 7)

PCLK0 : Bits in the PCLKR register

G1TM0, G1PO0

G1TM1, G1PO1

G1TM2, G1PO2

G1TM3, G1PO3

G1TM4, G1PO4

G1TM5, G1PO5

G1TM6, G1PO6

G1TM7, G1PO7

PWM

output

PWM

output

PWM

output

PWM

output

Base timer reset

(n+1)

Divider register

Edge

select

Digital

filter

Gate

function

Edge

select

Digital

filter

Gate

function

Edge

select

Digital

filter

Edge

select

Digital

filter

INPC10

INPC11

INPC16

(G1DV)

Ch0 to ch7

interrupt request signal

OUTC10

OUTC11

OUTC14

OUTC15

Prescaler

function

Prescaler

function

OUTC16

OUTC17

OUTC12

OUTC13

(Note 1)

Base timer

fBT1

Edge

select

Digital

filter

INPC12

Two-phase

pulse input

BCK1 to BCK0 : Bits in the G1BCR0 register

Request from INT1 pin

BTS

Request by matching G1PO0 register and base timer

Base timer over flow request

BCK1 to BCK0

10:fBT1

11: f1 or f2

DF1 to DF0

CTS1 to CTS0

DF1 to DF0

Base timer reset

Request by matching G1BTRR and base timer

CTS1 to CTS0

DF1 to DF0

Edge

select

Digital

filter

INPC13

DF1 to DF0

Edge

select

Digital

filter

INPC14

CTS1 to CTS0

DF1 to DF0

Edge

select

Digital

filter

INPC15

CTS1 to CTS0

INPC17

Digital

debounce

Base timer reset request

Base timer interrupt request

CTS1 to CTS0

1/2

PCLK0=0

PCLK0=1

f1 or f2

Main clock,

PLL clock,

On-chip

oscillator clock

10:fBT1

11: f1 or f2

10:fBT1

11: f1 or f2

10:fBT1

11: f1 or f2

10:fBT1

11: f1 or f2

10:fBT1

11: f1 or f2

10:fBT1

11: f1 or f2

10:fBT1

11: f1 or f2

Figure 13.1

shows the block diagram of the IC/OC.

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