M16CSLASH29 datasheet(129/499 Pages) RENESAS

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12. Timer A

page 105

Figure 12.6 ONSF Register, TRGSR Register, and CPSRF Register

Symbol

Address

After Reset

CPSRF

038116

0XXXXXXX2

Clock Prescaler Reset Flag

Bit Name

Function

Bit Symbol

b7 b6 b5 b4 b3 b2 b1 b0

Clock prescaler reset flag

Setting this bit to 1 initializes the

prescaler for the timekeeping clock.

(When read, its content is 0)

CPSR

Nothing is assigned. If necessary, set to 0.

When read, their contents are undefined

TA1TGL

Symbol

Address

After Reset

TRGSR

038316

0016

Timer A1 event/trigger

select bit

0 0: Input on TA1IN is selected (1)

0 1: TB2 is selected (2)

1 0: TA0 is selected (2)

1 1: TA2 is selected (2)

Trigger Select Register

Bit Name

Function

Bit Symbol

b7 b6 b5 b4 b3 b2 b1 b0

0 0: Input on TA2IN is selected (1)

0 1: TB2 is selected (2)

1 0: TA1 is selected (2)

1 1: TA3 is selected (2)

0 0: Input on TA3IN is selected (1)

0 1: TB2 is selected (2)

1 0: TA2 is selected (2)

1 1: TA4 is selected (2)

0 0: Input on TA4IN is selected (1)

0 1: TB2 is selected (2)

1 0: TA3 is selected (2)

1 1: TA0 is selected (2)

Timer A2 event/trigger

select bit

Timer A3 event/trigger

select bit

Timer A4 event/trigger

select bit

TA1TGH

TA2TGL

TA2TGH

TA3TGL

TA3TGH

TA4TGL

TA4TGH

b1 b0

b3 b2

b5 b4

b7 b6

TA1OS

TA2OS

TA0OS

One-shot Start Flag

Symbol

Address

After Reset

ONSF

038216

0016

Timer A0 one-shot start flag

Timer A1 one-shot start flag

Timer A2 one-shot start flag

Timer A3 one-shot start flag

Timer A4 one-shot start flag

TA3OS

TA4OS

Bit Name

Function

Bit Symbol

b7 b6 b5 b4 b3 b2 b1 b0

TA0TGL

TA0TGH

0 0: Input on TA0IN is selected(1)

0 1: TB2 overflow is selected (2)

1 0: TA4 overflow is selected (2)

1 1: TA1 overflow is selected (2)

Timer A0 event/trigger

select bit

b7 b6

The timer starts counting by setting

this bit to 1 while bits TMOD1 and

TMOD0 in the TAiMR register (i = 0

to 4) = 102 (= one-shot timer mode)

and the MR2 bit in the TAiMR

When read, its content is 0

Z-phase input enable bit

TAZIE

0: Z-phase input disabled

1: Z-phase input enabled

(b6-b0)

NOTES:

1. Make sure the PD7_1 bit in the PD7 register is set to 0 (input mode).

2. Overflow or underflow.

NOTES:

1. Make sure the port direction bits for the TA1IN to TA4IN pins are set to 0 ( input mode).

2. Overflow or underflow.

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