M16CSLASH29 datasheet(450/499 Pages) RENESAS

450 / 499 page

22. Usage Notes

page 426

22.4 Interrupts

22.4.1 Reading Address 0000016

Do not read the address 0000016 in a program. When a maskable interrupt request is accepted, the CPU

reads interrupt information (interrupt number and interrupt request priority level) from the address

0000016 during the interrupt sequence. At this time, the IR bit for the accepted interrupt is cleared to 0.

If the address 0000016 is read in a program, the IR bit for the interrupt which has the highest priority

among the enabled interrupts is cleared to 0. This causes a problem that the interrupt is canceled, or an

unexpected interrupt request is generated.

22.4.2 Setting the SP

Set any value in the SP(USP, ISP) before accepting an interrupt. The SP(USP, ISP) is cleared to 000016

after reset. Therefore, if an interrupt is accepted before setting any value in the SP(USP, ISP), the pro-

gram may go out of control.

_______

22.4.3 NMI Interrupt

_______

1. The NMI interrupt is invalid after reset. The NMI interrupt becomes effective by setting the PM24 bit in

_______

the PM2 register to “1”. Set the PM24 bit to "1" when a high-level signal ("H") is applied to the NMI pin.

_______

If the PM24 bit is set to "1" when a low-level signal ("L") is applied, NMI interrupt is generated. Once NMI

interrupt is enabled, it will not be disabled unless a reset is applied.

_______

2. The input level of the NMI pin can be read by accessing the P8_5 bit in the P8 register.

_______

3. When selecting NMI function, stop mode cannot be entered into while input on the NMI pin is low. This

_______

is because while input on the NMI pin is low the CM1 register’s CM10 bit is fixed to 0.

_______

4. When selecting NMI function, do not go to wait mode while input on the NMI pin is low. This is because

_______

when input on the NMI pin goes low, the CPU stops but CPU clock remains active; therefore, the current

consumption in the chip does not drop. In this case, normal condition is restored by an interrupt gener-

ated thereafter.

_______

5. When selecting NMI function, the low and high level durations of the input signal to the NMI pin must

each be 2 CPU clock cycles + 300 ns or more.

_______

6. When using the NMI interrupt for exiting stop mode, set the NDDR register to FF16 (disable digital

debounce filter) before entering stop mode.

22.4.4 Changing the Interrupt Generate Factor

If the interrupt generate factor is changed, the IR bit in the interrupt control register for the changed

interrupt may inadvertently be set to 1 (interrupt requested). If you changed the interrupt generate factor

for an interrupt that needs to be used, be sure to clear the IR bit for that interrupt to 0 (interrupt not

requested).

“Changing the interrupt generate factor” referred to here means any act of changing the source, polarity

or timing of the interrupt assigned to each software interrupt number. Therefore, if a mode change of any

peripheral function involves changing the generate factor, polarity or timing of an interrupt, be sure to

clear the IR bit for that interrupt to 0 (interrupt not requested) after making such changes. Refer to the

description of each peripheral function for details about the interrupts from peripheral functions.

Figure 22.2

shows the procedure for changing the interrupt generate factor.

M16C/29 датащи(PDF) 450 Page - Renesas Technology Corp

M16C/29 датащи(HTML) 450 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL