M16CSLASH29 datasheet(448/499 Pages) RENESAS

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22. Usage Notes

page 424

5. Wait until the main clock oscillation stabilization time, before switching the CPU clock source to the

main clock.

Similarly, wait until the sub clock oscillates stably before switching the CPU clock source to the sub

clock.

6. Suggestions to reduce power consumption

(a) Ports

The processor retains the state of each I/O port even when it goes to wait mode or to stop mode. A

current flows in active I/O ports. A dash current may flow through the input ports in high impedance

state, if the input is floating. When entering wait mode or stop mode, set non-used ports to input and

stabilize the potential.

(b) A/D converter

When A/D conversion is not performed, set the VCUT bit in ADiCON1 register to 0 (no Vref connec-

tion). When A/D conversion is performed, start the A/D conversion at least 1 µs or longer after setting

the VCUT bit to 1 (Vref connection).

Use the CM0 register CM02 bit to stop the unnecessary peripheral functions during wait mode.

However, because the peripheral function clock (fC32) generated from the sub-clock does not stop,

this measure is not conducive to reducing the power consumption of the chip. If low speed mode or

low power dissipation mode is to be changed to wait mode, set the CM02 bit to 0 (do not peripheral

function clock stopped when in wait mode), before changing wait mode.

(d) Switching the oscillation-driving capacity

Set the driving capacity to “LOW” when oscillation is stable.

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