4513 datasheet(27/97 Pages) RENESAS

27 / 97 page

4513/4514 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

(3) External interrupt control registers

• Interrupt control register I1

rupt. Set the contents of this register through register A with the

TI1A instruction. The TAI1 instruction can be used to transfer the

contents of register I1 to register A.

• Interrupt control register I2

rupt. Set the contents of this register through register A with the

TI2A instruction. The TAI2 instruction can be used to transfer the

contents of register I2 to register A.

Table 8 External interrupt control registers

I13

I12

I11

I10

I23

I22

I21

I20

Not used

Interrupt valid waveform for INT0 pin/

return level selection bit (Note 2)

INT0 pin edge detection circuit control bit

INT0 pin

timer 1 control enable bit

This bit has no function, but read/write is enabled.

Falling waveform (“L” level of INT1 pin is recognized with the SNZI1

instruction)/“L” level

Rising waveform (“H” level of INT1 pin is recognized with the SNZI1

instruction)/“H” level

One-sided edge detected

Both edges detected

Disabled

Enabled

Not used

Interrupt valid waveform for INT1 pin/

return level selection bit (Note 3)

INT1 pin edge detection circuit control bit

INT1 pin

timer 3 control enable bit

Notes 1: “R” represents read enabled, and “W” represents write enabled.

2: When the contents of I12 is changed, the external interrupt request flag EXF0 may be set. Accordingly, clear EXF0 flag with the SNZ0 instruction.

3: When the contents of I22 is changed, the external interrupt request flag EXF1 may be set. Accordingly, clear EXF1 flag with the SNZ1 instruction.

Interrupt control register I1

R/W

at RAM back-up : state retained

at reset : 00002

This bit has no function, but read/write is enabled.

Falling waveform (“L” level of INT0 pin is recognized with the SNZI0

instruction)/“L” level

Rising waveform (“H” level of INT0 pin is recognized with the SNZI0

instruction)/“H” level

One-sided edge detected

Both edges detected

Disabled

Enabled

Interrupt control register I2

R/W

at RAM back-up : state retained

at reset : 00002

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