4513 datasheet(52/97 Pages) RENESAS

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4513/4514 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

RAM BACK-UP MODE

The 4513/4514 Group has the RAM back-up mode.

When the EPOF and POF instructions are executed continuously,

system enters the RAM back-up state. The POF instruction is

equal to the NOP instruction when the EPOF instruction is not ex-

ecuted before the POF instruction.

As oscillation stops retaining RAM, the function of reset circuit and

states at RAM back-up mode, current dissipation can be reduced

without losing the contents of RAM. Table 20 shows the function

and states retained at RAM back-up. Figure 38 shows the state

transition.

(1) Identification of the start condition

Warm start (return from the RAM back-up state) or cold start (re-

turn from the normal reset state) can be identified by examining the

state of the power down flag (P) with the SNZP instruction.

(2) Warm start condition

When the external wakeup signal is input after the system enters

the RAM back-up state by executing the EPOF and POF instruc-

tions continuously, the CPU starts executing the program from

address 0 in page 0. In this case, the P flag is “1.”

(3) Cold start condition

The CPU starts executing the program from address 0 in page 0

when;

• reset pulse is input to RESET pin, or

• reset by watchdog timer is performed, or

• voltage drop detection circuit detects the voltage drop.

In this case, the P flag is “0.”

Table 20 Functions and states retained at RAM back-up

Function

Program counter (PC), registers A, B,

carry flag (CY), stack pointer (SP) (Note 2)

Contents of RAM

Port level

Timer control register W1

Timer control registers W2 to W4, W6

Clock control register MR

Interrupt control registers V1, V2

Interrupt control registers I1, I2

Timer 1 function

Timer 2 function

Timer 3 function

Timer 4 function

A-D conversion function

A-D control registers Q1, Q2

Voltage comparator function

Voltage comparator control register Q3

Serial I/O function

Serial I/O mode register J1

Pull-up control register PU0

Key-on wakeup control register K0

Direction register FR0

External 0 interrupt request flag (EXF0)

External 1 interrupt request flag (EXF1)

Timer 1 interrupt request flag (T1F)

Timer 2 interrupt request flag (T2F)

Timer 3 interrupt request flag (T3F)

Timer 4 interrupt request flag (T4F)

Watchdog timer flags (WDF1, WDF2)

Watchdog timer enable flag (WEF)

16-bit timer (WDT)

A-D conversion completion flag (ADF)

Serial I/O transmission/reception completion flag

(SIOF)

Interrupt enable flag (INTE)

RAM back-up

(Note 3)

O (Note 5)

(Note 3)

✕ (Note 4)

Notes 1:“O” represents that the function can be retained, and “✕” repre-

sents that the function is initialized.

Registers and flags other than the above are undefined at RAM

back-up, and set an initial value after returning.

2: The stack pointer (SP) points the level of the stack register and is

initialized to “7” at RAM back-up.

3: The state of the timer is undefined.

4: Initialize the watchdog timer with the WRST instruction, and then

execute the POF instruction.

5: The state is retained when the voltage comparator function is se-

lected with the voltage comparator control register Q3.

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