M38039G8HKP datasheet(86/92 Pages) RENESAS

86 / 92 page

Rev.1.10

Nov 14, 2005

Page 86 of 91

REJ03B0166-0110

3803 Group (Spec.H QzROM version)

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to change.

Notes on Interrupts

1. Change of relevant register settings

When the setting of the following registers or bits is changed, the

interrupt request bit may be set to “1”. When not requiring the

interrupt occurrence synchronized with these setting, take the

following sequence.

• Interrupt edge selection register (address 003A16)

• Timer XY mode register (address 002316)

• Timer Z mode register (address 002A16)

Set the above listed registers or bits as the following sequence.

Fig 4.

Sequence of changing relevant register

When setting the followings, the interrupt request bit may be set

to “1”.

• When setting external interrupt active edge

Concerned register:Interrupt edge selection register

(address 003A16)

Timer XY mode register (address 002316)

Timer Z mode register (address 002A16)

• When switching interrupt sources of an interrupt vector

address where two or more interrupt sources are allocated.

Concerned register: Interrupt source selection register (address

003916)

2. Check of interrupt request bit

When executing the BBC or BBS instruction to an interrupt

request bit of an interrupt request register immediately after this

bit is set to “0”, execute one or more instructions before

executing the BBC or BBS instruction.

Fig 5.

Sequence of check of interrupt request bit

If the BBC or BBS instruction is executed immediately after an

interrupt request bit of an interrupt request register is cleared to

“0”, the value of the interrupt request bit before being cleared to

“0” is read.

Set the interrupt edge select bit (active edge switch bit)

or the interrupt (source) select bit to “1”.

NOP (one or more instructions)

Set the corresponding interrupt enable bit to “0” (disabled).

Set the corresponding interrupt request bit to “0”

(no interrupt request issued).

Set the corresponding interrupt enable bit to “1” (enabled).

NOP (one or more instructions)

Clear the interrupt request bit to “0” (no interrupt issued)

Execute the BBC or BBS instruction

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