M38039G8HKP datasheet(50/92 Pages) RENESAS

50 / 92 page

Rev.1.10

Nov 14, 2005

Page 50 of 91

REJ03B0166-0110

3803 Group (Spec.H QzROM version)

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to change.

• Serial I/O3

Serial I/O3 can be used as either clock synchronous or

asynchronous (UART) serial I/O3. A dedicated timer is also

provided for baud rate generation.

(1) Clock Synchronous Serial I/O Mode

Clock synchronous serial I/O3 mode can be selected by setting

the serial I/O3 mode selection bit of the serial I/O3 control

For clock synchronous serial I/O, the transmitter and the receiver

must use the same clock. If an internal clock is used, transfer is

started by a write signal to the transmit/receive buffer register.

Fig 40. Block diagram of clock synchronous serial I/O3

Fig 41. Operation of clock synchronous serial I/O3

Serial I/O3 control register

Receive buffer register 3

Receive shift register 3

Clock control circuit

1/4

Baud rate generator 3

f(XIN)

1/4

Clock control circuit

Falling-edge detector

Transmit buffer register 3

Transmit shift register 3

Serial I/O3 status register

F/F

Address 003016

Receive buffer full flag (RBF)

Receive interrupt request (RI)

Shift clock

Serial I/O3 synchronous clock selection bit

Frequency division ratio 1/(n+1)

Address 002F16

BRG count source selection bit

Address 003016

Shift clock

Transmit shift completion flag (TSC)

Transmit buffer empty flag (TBE)

Transmit interrupt request (TI)

Transmit interrupt source selection bit

Address 003116

Address 003216

Data bus

P36/SCLK3

P34/RXD3

P35/TXD3

P37/SRDY3

(f(XCIN) in low-speed mode)

RBF = 1

TSC = 1

TBE = 0

TBE = 1

TSC = 0

Transfer shift clock

(1/2 to 1/2048 of the internal

clock, or an external clock)

Serial output TXD3

Serial input RXD3

Write pulse to receive/transmit

buffer register (address 003016)

Overrun error (OE)

detection

Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after the transmit

shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O3 control register.

2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output

continuously from the TXD pin.

3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1”.

Receive enable signal SRDY3

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