M38039G8HKP datasheet(66/92 Pages) RENESAS

66 / 92 page

Rev.1.10

Nov 14, 2005

Page 66 of 91

REJ03B0166-0110

3803 Group (Spec.H QzROM version)

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to change.

Fig 61. System clock generating circuit block diagram (Single-chip mode)

WIT

instruction

STP

instruction

Timing

φ (internal clock)

Main clock stop bit

1/2

1/4

XIN

XOUT

XCOUT

XCIN

Interrupt request

Interrupt disable flag l

Reset

Port XC

switch bit

“1”

“0”

Low-speed

mode

High-speed or

middle-speed mode

Middle-speed mode

High-speed or

low-speed mode

Main clock division ratio

selection bits (Note 1)

Main clock division ratio

selection bits (Note 1)

Notes1: Either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.

When low-speed mode is selected, set port XC switch bit (b4) to “1”.

2:f(XIN)/16 is supplied as the count source to the prescaler 12 at reset, the count source before executing the STP instruction is

supplied as the count source at executing STP instruction.

3: When bit 0 of MISRG is “0”, timer 1 is set “0116” and prescaler 12 is set “FF16” automatically. When bit 0 of MISRG is “1” , set the

appropriate value to them in accordance with oscillation stabilizing time required by the using oscillator because nothing is

automatically set into timer 1 and prescaler 12.

4: Although a feed-back resistor exists on-chip, an external feed-back resistor may be needed depending on conditions.

Prescaler 12

Timer 1

Reset or

STP instruction

(Note 2)

Reset

(Note 3)

(Note 4)

STP

instruction

Divider

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