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M38039G8HKP датащи(PDF) 62 Page - Renesas Technology Corp |
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M38039G8HKP датащи(HTML) 62 Page - Renesas Technology Corp |
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62 / 92 page ![]() Rev.1.10 Nov 14, 2005 Page 62 of 91 REJ03B0166-0110 3803 Group (Spec.H QzROM version) PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. RESET CIRCUIT To reset the microcomputer, RESET pin should be held at an “L” level for 16 cycles or more of XIN. Then the RESET pin is returned to an “H” level (the power source voltage should be between 1.8 V and 5.5 V, and the oscillation should be stable), reset is released. After the reset is completed, the program starts from the address contained in address FFFD16 (high-order byte) and address FFFC16 (low-order byte). Make sure that the reset input voltage is less than 0.29 V for VCC of 1.8 V. Fig 56. Reset circuit example Fig 57. Reset sequence VCC RESET VCC RESET Power source voltage detection circuit Example at VCC = 5 V 1.8 V 0 V 0 V VCC RESET 0.29 V or less RESET Internal reset Data φ Address SYNC XIN ? ? ? ? FFFC FFFD ADH,L ? ? ? ?ADL ADH Notes 1: The frequency relation of f(XIN) and f( φ) is f(XIN) = 8 • f(φ). 2: The question marks (?) indicate an undefined state that depends on the previous state. Reset address from the vector table. XIN : 10.5 to 18.5 clock cycles |
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