M38039G8HKP datasheet(46/92 Pages) RENESAS

46 / 92 page

Rev.1.10

Nov 14, 2005

Page 46 of 91

REJ03B0166-0110

3803 Group (Spec.H QzROM version)

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to change.

1. Notes when selecting clock synchronous serial I/O

1.1 Stop of transmission operation

•Note

Clear the serial I/O1 enable bit and the transmit enable bit to

“0” (serial I/O and transmit disabled).

•Reason

Since transmission is not stopped and the transmission circuit

is not initialized even if only the serial I/O1 enable bit is

cleared to “0” (serial I/O disabled), the internal transmission is

running (in this case, since pins TXD1, RXD1, SCLK1, and

SRDY1 function as I/O ports, the transmission data is not

output). When data is written to the transmit buffer register in

this state, data starts to be shifted to the transmit shift register.

When the serial I/O1 enable bit is set to “1” at this time, the

data during internally shifting is output to the TXD1 pin and an

operation failure occurs.

1.2 Stop of receive operation

•Note

Clear the receive enable bit to “0” (receive disabled), or clear

the serial I/O1 enable bit to “0” (serial I/O disabled).

1.3 Stop of transmit/receive operation

• Note

Clear both the transmit enable bit and receive enable bit to “0”

(transmit and receive disabled).

(when dat a is transmit ted and received i n the clock

synchronous serial I/O mode, any one of data transmission and

reception cannot be stopped.)

•Reason

In the clock synchronous serial I/O mode, the same clock is

used for transmission and reception. If any one of transmission

and reception is disabled, a bit error occurs because

transmission and reception cannot be synchronized.

In this mode, the clock circuit of the transmission circuit also

operates for data reception. Accordingly, the transmission

circuit does not stop by clearing only the transmit enable bit to

“0” (transmit disabled). Also, the transmission circuit is not

initialized by clearing the serial I/O1 enable bit to “0” (serial

I/O disabled) (refer to 1.1).

2. Notes when selecting clock asynchronous serial I/O

2.1 Stop of transmission operation

•Note

Clear the transmit enable bit to “0” (transmit disabled). The

transmission operation does not stop by clearing the serial

I/O1 enable bit to “0”.

•Reason

Since transmission is not stopped and the transmission circuit

is not initialized even if only the serial I/O1 enable bit is

cleared to “0” (serial I/O disabled), the internal transmission is

running (in this case, since pins TXD1, RXD1, SCLK1, and

SRDY1 function as I/O ports, the transmission data is not

output). When data is written to the transmit buffer register in

this state, data starts to be shifted to the transmit shift register.

When the serial I/O1 enable bit is set to “1” at this time, the

data during internally shifting is output to the TXD1 pin and an

operation failure occurs.

2.2 Stop of receive operation

•Note

Clear the receive enable bit to “0” (receive disabled).

2.3 Stop of transmit/receive operation

• Note 1 (only transmission operation is stopped)

Clear the transmit enable bit to “0” (transmit disabled). The

transmission operation does not stop by clearing the serial

I/O1 enable bit to “0”.

•Reason

Since transmission is not stopped and the transmission circuit

is not initialized even if only the serial I/O1 enable bit is

cleared to “0” (serial I/O disabled), the internal transmission is

running (in this case, since pins TXD1, RXD1, SCLK1, and

SRDY1 function as I/O ports, the transmission data is not

output). When data is written to the transmit buffer register in

this state, data starts to be shifted to the transmit shift register.

When the serial I/O1 enable bit is set to “1” at this time, the

data during internally shifting is output to the TXD1 pin and an

operation failure occurs.

• Note 2 (only receive operation is stopped)

Clear the receive enable bit to “0” (receive disabled).

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