M306V2EEFS datasheet(171/271 Pages) RENESAS

171 / 271 page

Rev.1.40

Oct 06, 2004 page 171 of 269

M306V2ME-XXXFP, M306V2EEFP

2.14.6 Data Slice Line Specification Circuit

(1) Specification of data slice line

This circuit decides a line on which caption data is superimposed. The line 21 (fixed), 1 appropriate

line for a period of 1 field (total 2 line for a period of 1 field), and both fields (F1 and F2) are sliced their

data. The caption position register (address 026616) is used for each setting (refer to Table 2.14.1).

The counter is reset at the falling edge of Vsep and is incremented by 1 every Hsep pulse. When the

counter value matched the value specified by bits 4 to 0 of the caption position register, this Hsep is

sliced.

The values of “0016” to “1F16” can be set in the caption position register (at setting only 1 appropriate

line). Figure 2.14.8 shows the signals in the vertical blanking interval. Figure 2.14.9 shows the caption

position register.

(2) Specification of line to set slice voltage

The reference voltage for slicing (slice voltage) is generated for the clock run-in pulse in the particular

line (refer to Table 2.14.1). The field to generate slice voltage is specified by bit 1 of data slicer control

(3) Field determination

The field determination flag can be read out by bit 3 of data slicer control register 2. This flag change

at the falling edge of Vsep.

Figure 2.14.8 Signals in vertical blanking interval

Video signal

Vertical blanking interval

Composite video

signal

Count value to be set in the caption position register (“0F16” in this case)

Hsep

Vsep

Hsep

Magnified drawing

Clock run-in

Start bit + 16-bit data

Start bit

Window for

deteminating

clock-run-in

Composite video

signal

Line 21

1 appropriate line is set by

the caption position register

(when setting line 19)

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