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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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M306V2EEFS датащи(PDF) 53 Page - Renesas Technology Corp |
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M306V2EEFS датащи(HTML) 53 Page - Renesas Technology Corp |
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53 / 271 page  Rev.1.40 Oct 06, 2004 page 53 of 269 M306V2ME-XXXFP, M306V2EEFP 2.7.5 Interrupt Control Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the priority to be accepted. What is described here does not apply to non-maskable interrupts. Enable or disable a non-maskable interrupt using the interrupt enable flag (I flag), interrupt priority level selection bit, or processor interrupt priority level (IPL). Whether an interrupt request is present or absent is indicated by the interrupt request bit. The interrupt request bit and the interrupt priority level selection bit are located in the interrupt control register of each interrupt. Also, the interrupt enable flag (I flag) and the IPL are located in the flag register (FLG). Figure 2.7.3 shows the interrupt control registers. |
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