M306V2EEFS datasheet(30/271 Pages) RENESAS

30 / 271 page

Rev.1.40

Oct 06, 2004 page 30 of 269

M306V2ME-XXXFP, M306V2EEFP

Figure 2.4.4 Chip select control register

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Table 2.4.5 Operation of RD, WR, and BHE signals

(3) Read/write signals

With a 16-bit data bus (BYTE pin =“L”), bit 2 of the processor mode register 0 (address 000416) select

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the combinations of RD, BHE, and WR signals or RD, WRL, and WRH signals. With an 8-bit data bus

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(BYTE pin = “H”), use the combination of RD, WR, and BHE signals. (Set bit 2 of the processor mode

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After a reset has been cancelled, the combination of RD, WR, and BHE signals is automatically se-

lected.

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When switching to the RD, WRL, and WRH combination, do not write to external memory until bit 2 of

the processor mode register 0 (address 000416) has been set (Note).

Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of

the protect register (address 000A16) to “1”.

Function

Bit symbol

Bit name

Chip select control register

Symbol

Address

When reset

CSR

000816

0116

CS1

CS0

CS3

CS2

CS0 output enable bit

CS1 output enable bit

CS2 output enable bit

CS3 output enable bit

CS1W

CS0W

CS3W

CS2W

CS0 wait bit

CS1 wait bit

CS2 wait bit

CS3 wait bit

0 : Chip select output disabled

(Normal port pin)

1 : Chip select output enabled

0 : Wait state inserted

1 : No wait state

Status of external data bus

Read data

Write 1 byte of data to even address

Write 1 byte of data to odd address

Write data to both even and odd addresses

WRH

WRL

Data bus width

16-bit

(BYTE = “L”)

Status of external data bus

BHE

Write 1 byte of data to odd address

Read 1 byte of data from odd address

Write 1 byte of data to even address

Read 1 byte of data from even address

Data bus width

H / L

8-bit

(BYTE = “H”)

Write data to both even and odd addresses

Read data from both even and odd addresses

Write 1 byte of data

Read 1 byte of data

16-bit

(BYTE = “L”)

Not used

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Table 2.4.4 Operation of RD, WRL, and WRH signals

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