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M306V2EEFS датащи(PDF) 54 Page - Renesas Technology Corp |
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M306V2EEFS датащи(HTML) 54 Page - Renesas Technology Corp |
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54 / 271 page ![]() Rev.1.40 Oct 06, 2004 page 54 of 269 M306V2ME-XXXFP, M306V2EEFP Figure 2.7.3 Interrupt control registers Symbol Address When reset INTiIC(i = 0, 1) 005D16, 005E16 XX00?0002 IIC1IC 004916 XX00?0002 Bit name Function Bit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 ILVL0 IR POL Nothing is assigned. In an attempt to write to these bits, write “0.” The value, if read, turns out to be indeterminate. Interrupt priority level select bit Interrupt request bit Polarity select bit (Note 2) Reserved bit 0: Interrupt not requested 1: Interrupt requested 0 : Selects falling edge 1 : Selects rising edge Must always be set to “0” ILVL1 ILVL2 Notes 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). 2: Bit 4 at address 004916 is invalid. Must always be set to “0.” 3: To rewrite the interrupt control register, do so at a point that does not generate the interrupt register for that register For details see the precautions for interrupts (Note 1) Interrupt control register b7 b6 b5 b4 b3 b2 b1 b0 Bit name Function Bit symbol W R Symbol Address When reset OSDiIC(i = 1, 2) 004416, 004816 XXXX?0002 BCNIC 004A16 XXXX?0002 DMiIC(i = 0, 1) 004B16, 004C16 XXXX?0002 IIC0IC 004D16 XXXX?0002 ADIC 004E16 XXXX?0002 SiTIC(i = 0 , 2) 005116, 004F16 XXXX?0002 SiRIC(i = 0 , 2) 005216, 005016 XXXX?0002 DSIC 005316 XXXX?0002 VSYNCIC 005416 XXXX?0002 TAiIC(i = 0 to 4) 005516 to 005916 XXXX?0002 TBiIC(i = 0 to 2) 005A16 to 005C16 XXXX?0002 ILVL0 IR Interrupt priority level select bit Interrupt request bit 0 : Interrupt not requested 1 : Interrupt requested ILVL1 ILVL2 Nothing is assigned. In an attempt to write to these bits, write “0.” The value, if read, turns out to be indeterminate. (Note) Notes 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). 2: To rewrite the interrupt control register, do so at a point that does not generate the interrupt register for that register. For details, see the precautions for interrupts. 0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 b2 b1 b0 0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 b2 b1 b0 0 |
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